Shulou(Shulou.com)06/03 Report--

Development environment

Host: Windows7 64bits system

Development board: Ami MDK972

Software environment: RealEvo-IDE3.0

NAND Flash: S34ML02G100TF100

S34ML02G100TF100 chip parameters

Density:2 Gbit

Input / Output Bus Width: 8-bits

Page Size:2112 (2048 + 64) bytes; 64 bytes is spare area

Block Size: 64 Pages;128k + 4k bytes

Plane Size: 1024 Blocks per Plane;128M + 4m bytes

Device Size: 2 Planes per Device or 256 Mbyte

NAND controller structure

The NAND controller for NUC970 is included in the FMI. FMI is divided into DMA unit and FMI unit. For NAND, a single DMA channel and hardware ECC are supported, as shown in figure 2-1.

Figure 2-1 NUC970 NAND controller

Technology implementation driven framework

The driver framework of NAND Flsh in SylixOS is shown in figure 3-1. The NAND universal driver is mainly in fs/mtd/nand/nand_base.c, which contains the general operations of NAND. The driver engineer needs to implement the hardware-related driver layer structure (nand_chip) on the basis of the NAND universal driver, which contains the specific hardware-related control and operation functions, as well as related hardware parameters and configuration information. MTD layer and file system, SylixOS has been fully implemented, does not need to be implemented by driver engineers.

Figure 3-1 NAND driver framework

Framework implementation

The NAND driver needs to complete the NAND controller, ECC configuration, NAND-related operation functions and file system mount. If you use hardware ECC, you generally define your own OOB layout. The operation implemented by the NUC970 driver is shown in listing 3-1.

Listing 3-1 NAND implementation framework

NandchipNand- > cmd_ctrl = hwControl; nandchipNand- > cmdfunc = nandCommand; nandchipNand- > dev_ready = devReady; nandchipNand- > select_chip = chipSelect; nandchipNand- > read_byte = nandReadByte; nandchipNand- > write_buf = nandWriteBuf; nandchipNand- > read_buf = nandReadBuf; nandchipNand- > chip_delay = 50; nandchipNand- > ecc.mode = NAND_ECC_HW_OOB_FIRST NandchipNand- > ecc.hwctl = nandEnableHwEcc; nandchipNand- > ecc.calculate = nandCalculateEcc; nandchipNand- > ecc.correct = nandCorrectData; nandchipNand- > ecc.write_page = nandWritePageHwEcc; nandchipNand- > ecc.read_page = nandReadPageHwEccOobFirst; nandchipNand- > ecc.read_oob = nandReadoobHwEcc;nandchipNand- > ecc.layout = & _ Gpnuc970nandoob; controller initialization

The initialization of the controller mainly realizes the operation of module clock enabling, pin reuse, timing setting, chip selection, unwriting protection, page size, software reset and so on.

ECC configuration

ECC configuration mainly sets the size of the redundancy area, protects the first 3 bytes, automatically writes the check value to NAND, sets the algorithm level, ECC enables and other operations.

Function cmd_ctrl

This function mainly controls ALE/CLE/nCE and is used to write commands and addresses at the same time.

Program listing 3-2 command control function

Static VOID hwControl (struct mtd_info * pMtd, INT iCmd, UINT uiCtrl) {struct nand_chip * pChip = pMtd- > priv; if (uiCtrl & NAND_CTRL_CHANGE) {ULONG IO_ADDR_W = (ULONG) REG_NANDDATA; if ((uiCtrl & NAND_CLE)) {IO_ADDR_W = REG_NANDCMD } if ((uiCtrl & NAND_ALE)) {IO_ADDR_W = REG_NANDADDR;} pChip- > IO_ADDR_W = (VOID *) IO_ADDR_W;} if (iCmd! = NAND_CMD_NONE) {writeb (iCmd, pChip- > IO_ADDR_W);}} function cmdfunc

This function mainly realizes the function of writing commands to the chip, and the specific write operation is realized by calling the cmd_ctrl function in the default function provided by the system. Because the controller of NUC970 needs to set the EOA bit manually in the last address cycle, the default function cannot be used, and the difference code is shown in listing 3-3:

Program listing 3-3 command function difference code

Writel ((iColumn > > BUS_WIDTH) | NANDADDR_EOA, REG_NANDADDR); function dev_ready

This function is mainly used to obtain the ready/busy pin status of the device. If the function pointer is set to NULL that the ready/busy pin state cannot be obtained, the ready/busy information needs to be read by reading the status register of the NAND chip. The code implementation is shown in listing 3-4.

Listing 3-4 gets the NAND status

Return ((readl (REG_NANDINTSTS) & NANDINTSTS_RB0_Status)? 1: 0); function read_byte

The function is to read a byte from the NAND chip, and the code is shown in listing 3-5.

Listing 3-5 reads a byte from NAND

Return ((UCHAR) readl (REG_NANDDATA)); function write_buf

The function is to write data from a buffer to the NAND chip. The code implementation is shown in listing 3-6.

Listing 3-6 writes buffer data to NAND

For (I = 0; I)

< iLen; i++) { writel(pucbuf[i], REG_NANDDATA); }函数read_buf 该函数功能为从NAND芯片读数据到一个缓冲区。代码实现如程序清单 3-7所示。 程序清单 3-7 读数据到缓冲区 for (i = 0; i < iLen; i++) { writel(pucbuf[i], REG_NANDDATA); }函数ecc.hwctl 该函数用于控制硬件ECC发生器，只有在使用硬件ECC时实现。本例的硬件校验在传输中实现，因此该函数为空实现。 函数ecc.calculate 该函数用于ECC计算，或从ECC硬件中读回。本例的硬件校验在传输中实现，因此该函数为空实现。 函数ecc.correct 该函数用于ECC校正。本例的硬件校验在传输中实现，因此该函数为空实现。 函数ecc.write_page 该函数主要实现带ECC的写一页数据到NAND芯片。在传输的过程中，ECC电路会自动计算ECC校验值，并存储到控制器分配的寄存器组中。完成传输后寄存器组中的OOB数据会根据设置自动写进NAND芯片。实现流程如程序清单 3-8所示。 程序清单 3-8 带硬件ECC的写页 static INT nandWritePageHwEcc (struct mtd_info *pMtd, struct nand_chip *pChip, const UCHAR *pucBuf, INT iOobRequired){ UCHAR *pucEccCalc = pChip->

Buffers- > ecccalc; UINT uiEccBytes = pChip- > ecc.layout- > eccbytes; register CHAR * pcPtr = (CHAR *) REG_NANDRA0; memset ((VOID *) pcPtr, 0xFF, pMtd- > oobsize); memcpy ((VOID *) pcPtr, (VOID *) pChip- > oob_poi, pMtd- > oobsize-pChip- > ecc.total); nandDmaTransfer (pMtd, pucBuf, pMtd- > writesize, 0x1) / * * Copy parity code in SMRA to calc * / memcpy ((VOID *) pucEccCalc, (VOID *) (REG_NANDRA0 + (pMtd- > oobsize-pChip- > ecc.total), pChip- > ecc.total) / * * Copy parity code in calc to oob_poi * / memcpy ((VOID *) (pChip- > oob_poi + uiEccBytes), (VOID *) pucEccCalc, pChip- > ecc.total); return 0;}

Function ecc.read_page

This function mainly realizes reading a page of data from the NAND chip with ECC check. This example is a hardware ECC, which needs to read out the OOB data to the register group assigned by the controller. In the process of data transmission, the ECC circuit calculates the ECC check value, compares it with the value in the register group, checks for errors, and locates and calculates the correction value. If an error occurs, the program needs to correct the error according to the error location and error value. The specific process is shown in listing 3-9:

Program listing 3-9 Page read with ECC

Static INT nandReadPageHwEccOobFirst (struct mtd_info * pMtd, struct nand_chip * pChip, UCHAR * ucBuf, INT iOobRequired) INT iPage) {INT iEccSize = pChip- > ecc.size CHAR * pcPtr = (CHAR *) REG_NANDRA0; / * * At first, read the OOB area * / nandCommand (pMtd, NAND_CMD_READOOB, 0, iPage); nandReadBuf (pMtd, pChip- > oob_poi, pMtd- > oobsize); / * * Second, copy OOB data to SMRA for page read * / memcpy ((VOID *) pcPtr, (VOID *) pChip- > oob_poi, pMtd- > oobsize) / * * Third, read data from nand * / nandCommand (pMtd, NAND_CMD_READ0, 0, iPage); nandDmaTransfer (pMtd, ucBuf, iEccSize, 0x0); / * * Fouth, restore OOB data from SMRA * / memcpy ((VOID *) pChip- > oob_poi, (VOID *) pcPtr, pMtd- > oobsize); return 0;} function ecc.read_oob

This function mainly realizes reading OOB data from the chip. The implementation process is shown in listing 3-10.

Program listing 3-10 read OOB area data with hardware ECC

Static INT nandReadoobHwEcc (struct mtd_info * pMtd, struct nand_chip * pChip, INT iPage) {CHAR * cPtr = (char *) REG_NANDRA0; / * * At first, read the OOB area * / nandCommand (pMtd, NAND_CMD_READOOB, 0, iPage); nandReadBuf (pMtd, pChip- > oob_poi, pMtd- > oobsize) / * * Second, copy OOB data to SMRA for page read * / memcpy ((VOID *) cPtr, (VOID *) pChip- > oob_poi, pMtd- > oobsize); return 0;} ecc.layout

Nand_ecc is the ECC layout control structure. Through this structure, the number of bits and positions of ECC in the OOB area, the number of available bits and the number of free bits are configured. This example implements the layout control of the OOB area by calling the code in listing 3-11 of the program.

Listing 3-11 OOB area layout

Static VOID oobTableLayout (struct nand_ecclayout * pNandOOBTbl, INT iOobSize, INT iEccBytes) {pNandOOBTbl- > eccbytes = iEccBytes; pNandOOBTbl- > oobavail = iOobSize-DEF_RESERVER_OOB_SIZE_FOR_MARKER-iEccBytes; pNandOOBTbl- > oobfree [0] .offset = DEF_RESERVER_OOB_SIZE_FOR_MARKER; / * Bad block marker size * / pNandOOBTbl- > oobfree [0] .length = iOobSize-iEccBytes-pNandOOBTbl- > oobfree [0] .offset;} File system mount

Under SylixOS, NAND Flash usually mounts the YAFFS file system and divides it into n0 and N1 partitions, where n0 partition is used as boot partition and N1 as application partition. The mount process is shown in listing 3-12.

Program listing 3-12 file system mount

Yaffs_mtd_drv_install (& _ GyaffsdevBootDev); yaffs_mtd_drv_install (& _ GyaffsdevCommDev); yaffs_add_device (& _ GyaffsdevBootDev); / * add to yaffs device table * / yaffs_add_device (& _ GyaffsdevCommDev); / * add to yaffs device table * / yaffs_mount (cBootDevName); yaffs_mount (cCommDevName); Resources

None.

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