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This article mainly introduces "how is MMU segment mapping". In daily operation, I believe many people have doubts about how MMU segment mapping is. The editor consulted all kinds of materials and sorted out simple and easy-to-use operation methods. I hope it will be helpful to answer the doubts of "how MMU segment mapping is". Next, please follow the editor to study!

First of all, the schematic diagram of segment mapping is as follows:

The routine consists of five files:

Head.s- entry program

Mmu.lds- connection file

Init.c- initialization file

Makefile- compile connection

Leds.c- main program

Start with the entry function:

@ * * @ File:head.S@ function: set SDRAM, copy the second part of the code to SDRAM, set the page table, and start MMU Then jump to SDRAM to continue to execute @ * .text.global _ start_start: ldr sp, = 4096 @ to set the stack pointer The following are all C functions. You need to set the stack bl disable_watch_dog @ to close WATCHDOG before calling. Otherwise, CPU will continue to restart bl memsetup @ to set up the storage controller to copy the second part of the code to SDRAM using SDRAM bl copy_2th_to_sdram @-Note 1 bl create_page_table @ Settings page table-Note 2 Bl mmu_init @ starts MMU-Note 3 ldr sp = 0xB4000000 @ reset stack pointer Point to the top of SDRAM (using a virtual address) ldr pc, = 0xB0004000 @ jump to SDRAM and continue to execute the second part of code halt_loop: B halt_loop

Note 1:

/ / file: init.cvoid copy_2th_to_sdram (void) {unsigned int * pdwSrc = (unsigned int *) 2048; unsigned int * pdwDest = (unsigned int *) 0x30004000; while (pdwSrc

< (unsigned int *)4096) { *pdwDest = *pdwSrc; pdwDest++; pdwSrc++; }}//file: mmu.ldsSECTIONS { firtst 0x00000000 : { head.o init.o } second 0xB0004000 : AT(2048) { leds.o }} 由mmu.lds可知, 第二部分的代码链接地址为2048, 加载地址为 0xB000 4000. 而init.c中将第二段的代码放到了 0x3000 4000. 我们利用mmu将 物理地址0x3000 4000 映射到 虚拟地址0xB000 4000. 注释2: void create_page_table(void){/* * 用于段描述符的一些宏定义 */ #define MMU_FULL_ACCESS (3 >

20)) = (physicaladdr & 0xFFF00000) |\ MMU_SECDESC_WB; virtuladdr + = 0x1000000; / / the segment descriptor corresponds to 1m space, so add 0x100000 physicaladdr + = 0x1000000;}} each time

Mmu_tlb_base is defined as the unsigned long type, which is exactly the same size as the page table descriptor in 4byte. The value of mmu_tlb_base is 0x3000 0000, indicating that the first-level page table is placed at the beginning of SDRAM.

The sentence that best represents the structure of the page table is:

* (mmu_tlb_base + (virtuladdr > > 20)) = (physicaladdr & 0xFFF00000) | MMU_SECDESC_WB

[31:20] of MVA is equal to the page table index (table index), and the corresponding code is (virtualaddr > > 20)

PA [31:20] equals [31:20] of the paragraph descriptor, with the corresponding code (physicaladdr & 0xFFF00000)

To put it simply, it is to find the segment descriptor in the first-level page table according to the MVA and TTB registers. The segment descriptor stores the actual physical address, and our program is only 1. 0. Configured with TTB register 2. The physical address is stored in the segment descriptor

Also, the area we are mapping is 0x3000 0000 to 0xB000 0000, so why does the code start with 0x3000 4000? Because there are up to 4096 page table items, each 4byte, a total of 16k, so the first 16k is reserved to prevent the page table area from being overwritten.

Note 3:

The mmu section does not explain his various configurations in detail. The most important thing is to write our fixed page table base address 0x3000 0000 into the cp15 page table base register.

/ * * start MMU * / void mmu_init (void) {unsigned long ttb = 0x30000000 _ _ asm__ ("mov R0, # 0\ n"mcr p15,0, R0, c7, c7, 0\ n" / * invalidate ICaches and DCaches * / "mcr p15,0, R0, c7, c10, 4\ n" / * drain write buffer on v4 * / "mcr p15,0, R0, c8, c7, 0\ n" / * invalidate instructions, data TLB * / "mov R4" % 0\ n "/ * R4 = page table base address * /" mcr p15,0, R4, c2, c0,0\ n "/ * set the page table base register * /" mvn R0, # 0\ n "" mcr p15,0, R0, c3, c0,0\ n "/ * the domain access control register is set to 0xFFFFFFFF * No permission check * / / * for the control register, read out its value first and modify the bits of interest on this basis * then write * / "mrc p15,0, R0, C1, c0,0\ n" / * read out the value of the control register * / / * the low 16-bit meaning of the control register means: .RVI.. RS B. Cam * R: indicates the algorithm used when swapping out entries in Cache, * 0 = Random replacement;1 = Round robin replacement * V: indicates the location of the exception vector table, * 0 = Low addresses = 0x00000000X 1 = High addresses = 0xFFFF0000 * I: 0 = close ICaches 1 = enable ICaches * R, S: used to determine the access to memory together with the descriptors in the page table * B: 0 = CPU is small byte order; 1 = CPU is large byte order * C: 0 = off DCaches;1 = turn on DCaches * A: 0 = no address alignment check is performed during data access; 1 = address alignment check is performed during data access * M: 0 = off MMU 1 = turn on MMU * / / * * first clear the unwanted bits, then reset them if necessary * / / * .RVI.. RS B. Cam * / "bic R0, R0, # 0x3000\ n" / * .11.... .... .... Clear V, I bit * / "bic R0, R0, # 0x0300\ n" / *. .. 11.... .... Clear R, S bit * / "bic R0, R0, # 0x0087\ n" / *. .... 1... .111 clear the bit * / "orr R0, R0, # 0x0002\ n" / * required by the B/C/A/M * / / * setting. .... .... .. 1. Enable alignment check * / "orr R0, R0, # 0x0004\ n" / *. .... .... .1.. Open DCaches * / "orr R0, R0, # 0x1000\ n" / *. 1. .... .... Open ICaches * / "orr R0, R0, # 0x0001\ n" / *. .... .... .. 1 enable MMU * / "mcr p15,0, R0, C1, c0,0\ n" / * write the modified value to the control register * /: / * No output * /: "r" (ttb)) } / / leds.c: lighting 4 LED / * in a loop belongs to the second part of the program. When MMU is enabled, use virtual address * / # define GPFCON (* (volatile unsigned long *) 0xA0000050) / / physical address 0x56000050 corresponding virtual address 0xA0000050 # define GPFDAT (* (volatile unsigned long *) 0xA0000054) / / physical address 0x56000054 corresponding virtual address 0xA0000054 # define GPF4_out (1)

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