Shulou(Shulou.com)06/02 Report--

Today I will show you how to analyze DDR2 in FPGA design. The content of the article is good. Now I would like to share it with you. Friends who feel in need can understand it. I hope it will be helpful to you. Let's read it along with the editor's ideas.

DDR2 IP system block diagram

2. IP parameter setting

1) clock setting

PLL reference clock freqency is a reference input clock, usually provided by an external crystal oscillator or external PLL output

Memory clock freqency is the DDR clock. Generally speaking, CYCLONE IV can only support 200m as fast as possible, depending on different models and BANK.

Controller data rate has Full and Half modes. When you choose Half mode, Local interface width will double.

2) Select Memory Presets

Select the corresponding DDR2 according to the type of presets in the circuit. Here we only focus on the setting of the address under the Full rate.

Under Full rate:

Local_address is 25 bits wide

Local_address [23:11] = row address [13:0]

Local_address [10:9] = bank address [1:0]

Local_address [8:0] = column address [9:1]

The width of the local data is twice that of the bus data, so the IP core ignores the lowest bit of the column

3) set local parameters

Local-to-Memory Address Mapping: set address mapping, which needs to be consistent with the above address mapping instructions

Local Maximum Burst Count: set to 32 to improve the efficiency of reading and writing

3. Instantiate IP kernel

Ddr2_64bit ddr2_64bit_inst (.local _ address (local_address), .local _ write_req (local_write_req), .local _ read_req (local_read_req), .local _ burstbegin (local_burstbegin) .local _ wdata (local_wdata), .local _ be (16'hffff), .local _ size (BURST_LEN), .global _ reset_n (rst_n) .pll _ ref_clk (ref_clk), .soft _ reset_n (rst_n), .local _ ready (local_ready), .local _ rdata (local_rdata) .local _ rdata_valid (local_rdata_valid), .local _ refresh_ack (), .local _ init_done (local_init_done), .reset _ phy_clk_n () .phy _ clk (phy_clk), .aux _ full_rate_clk (), .aux _ half_rate_clk (), .reset _ request_n () .mem _ odt (mem_odt), .mem _ cs_n (mem_cs_n), .mem _ cke (mem_cke), .mem _ addr (mem_addr) .mem _ ba (mem_ba), .mem _ ras_n (mem_ras_n), .mem _ cas_n (mem_cas_n), .mem _ we_n (mem_we_n) .mem _ dm (mem_dm), .mem _ clk (mem_clk), .mem _ clk_n (mem_clk_n), .mem _ dq (mem_dq) .mem _ dqs (mem_dqs))

4. Design read-write test module

/ /-ddr2 read and write operation-reg [25: 0] local_address;reg local_burstbegin;reg local_read_req;reg local_write_req;reg [127 local_wdata;reg] local_wdata;reg [2:0] local_state;reg [7:0] local_cnt;reg [127 local_wdata;reg] local_readdata Parameter IDLE = 0, IDLE0 = 1, BURST_WRITE = 2, IDLE1 = 3, BURST_READ = 4, END = 5 Always @ (posedge phy_clk) if (~ rst_n) begin local_state

Welcome to subscribe "Shulou Technology Information " to get latest news, interesting things and hot topics in the IT industry, and controls the hottest and latest Internet news, technology news and IT industry trends.