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What's the use of Makefile in C++?

2025-03-05 Update From: SLTechnology News&Howtos shulou NAV: SLTechnology News&Howtos > Development >

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In this article, the editor introduces in detail the "what is the use of Makefile in C++" with detailed contents, clear steps and proper handling of details. I hope that this article "what is the use of Makefile in C++" can help you solve your doubts.

Introduction

Makefile is a script file that specifies how to compile and link the program, which will be executed when the make command is executed. IDE in the window environment, such as visual studio, has integrated this function and does not need to care about the compilation rules of the program. It is often used in linux development. First of all, you need to know a tool make.

Make is a command tool for interpreting instructions in Makefile, which is integrated with common IDE. Currently, the make version of centos 7.3 GNU is 3.82.

Rules

Target files: dependent fil

[Tab] system instruction 1 (Note: there must be a tab before the system instruction)

Use

3.1 easy to use

Existing files main.cpp test.cpp test.h three files, say something about Makefile to implement incremental compilation (when one of the files changes, recompile the file)

Helloworld: main.otest.o gathers + main.otest.o-o helloworldmain.o: main.cpp test.h gathers +-c main.cpp-o main.otest.o: test.cpp test.h gathers +-c test.cpp-o test.oclean: rm * .o helloworld

3.2 use annotations, variables, and functions in makefile

Note:

Precede the line with a "#" sign, such as # main.o test.o + main.o test.o-o helloworld to indicate that the line is annotated

Variables:

Define a variable with = and assign a value (spaces can be added on both sides of the equal sign)

Append a string with + =

Use $(A) to get the value of the variable

Example:

A = src echo $(A) @ echo $(A) # # only outputs the results of echo, but does not show the commands executed

Special variables:

$@ target file

$^ dependency list

$< first item in the dependency list

Function:

There are some predefined functions in Makefile in the form:

$(function name argument list)

Parameter list: separated by comma

Function names and parameters are separated by spaces

# get the current directory path

PWD = $(shell pwd)

# get all .cpp files in the current directory

CXX_SOURCES = $(wildcard * .cpp)

# get all the compiled target files of all .cpp files in the current directory. O

CXX_OBJECTS = $(patsubst * .cpp * .o, $(CXX_SOURCES))

3.3.The Makefile in Optimization 3.1

EXE = helloworldGCC = galleys $(EXE): main.o test.o $(GCC) $^-o $(EXE) main.o: main.cpp test.h $(GCC)-c $<-o $@ test.o: test.cpp test.h $(GCC)-c $<-o $@ clean: rm * .o $(EXE)

3.4.The Makefile in optimization 3.3,

Continue to optimize Makefile, add folders, put the source code into src and lib folders, and maintain incremental compilation, that is, a general template for Makefile

EXE = helloworldGCC = g++SUBDIR = src libCPP_SOURCES = $(foreach dir, $(SUBDIR), $(wildcard $(dir) / * .cpp)) CPP_OBJECTS = $(patsubst% .cpp,% .o, $(CPP_SOURCES)) DEP_FILES = $(patsubst% .o,% .d $(CPP_OBJECTS)) $(EXE): $(CPP_OBJECTS) $(GCC) $(CPP_OBJECTS)-o $@% .o:% .cpp $(GCC)-c-MMD $<-o $@-include $(DEP_FILES) clean: rm $(CPP_OBJECTS) $(EXE) This article "what is the use of Makefile in C++" has been introduced, and if you want to master the knowledge of this article, you still need to practice and use it. If you want to know more about the article, please follow the industry information channel.

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