Shulou(Shulou.com)06/01 Report--

This article mainly introduces "how to use Virtual clock". In daily operation, I believe many people have doubts about how to use Virtual clock. The editor consulted all kinds of materials and sorted out simple and easy-to-use operation methods. I hope it will be helpful to answer the doubts about "how to use Virtual clock". Next, please follow the editor to study!

What is virtual clock?

A clock that has no source (clock source) defined. Commonly used to constrain interface timing, the associated sdc command is set_input_delay set_output_delay. (correspondingly, the clock that defines the source (clock source) is real clock.)

Example:

Create_clock-name VCLK-period 10

Why use virtual clock?

Simply put, the advantage of setting up virtual clock is that you can specify the clock network delay of clock without affecting real clock.

We know that clock latency includes clock source latency and clock network delay. When there is no clock tree in BLOCK, clock network delay is equal to 0. at this time, for the path from RegA to PORT, the effect is the same with virtual clock or real clock.

However, when BLOCK reaches the CTS stage, because there is clock network delay inside BLOCK, and RegB is just a virtual register, his clock tree does not exist, so clock network delay is 0, which causes the timing path from RegA to PORT to become too strict (in contrast, the setup check from input to path in internal registers is too optimistic). Then we can set source latency on RegB. Unfortunately, however, if you are using real clock, it will inevitably lead to a corresponding change in the source latency of RegA's clock. At this time, the benefits of virtual clock are reflected.

Example: constrain PORT with virtual clock

Set_output_delay-clock [get_clocks VCLK]-max 1 [get_port PORT]-add

Suppose we use virtual clock for RegB (as in the example), after CTS, we can add latency:set_clock_latency-clock VCLK $clock_network_delay to VCLK.

For real clock, after CTS, ideal clock is set to propgated clock (set_propagated_clock), so for real clck, clock network delay cannot be set with set_clock_latency.

Of course, there is a way to solve this problem with real clock, which is to modify input delay or output delay. For Figure1, you can reduce output delay by the same number as clock network delay.

Since today's PR tools automatically perform update io latency actions after CTS, we don't have to use a real clock at all, and then fix port's input delay or output delay after CTS.

At this point, the study on "how to use Virtual clock" is over. I hope to be able to solve your doubts. The collocation of theory and practice can better help you learn, go and try it! If you want to continue to learn more related knowledge, please continue to follow the website, the editor will continue to work hard to bring you more practical articles!

Welcome to subscribe "Shulou Technology Information " to get latest news, interesting things and hot topics in the IT industry, and controls the hottest and latest Internet news, technology news and IT industry trends.