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This article shows you how to use the Signal tap logic analyzer, the content is concise and easy to understand, it can definitely brighten your eyes. I hope you can get something through the detailed introduction of this article.

Signal tap logic analyzer is used

In the previous design and development, the data of an intermediate unit was obtained by using modelsim, and the input was also given by the designer himself in testbench. However, in practical application, the external input signal is not necessarily the same as the input signal we describe in testbench, which may lead to the success of RTL simulation, but the lower board test fails.

The signal tap logic analyzer captures and displays the real-time signal behavior in the FPGA design so that it can check the behavior of internal signals during normal device operation without the need for additional Imax O pins or external laboratory equipment.

During data acquisition, the memory module in the device stores the collected data and then transmits the data to the logic analyzer through the JTAG communication cable.

The following figure shows the task flow of signal tap logic analyzer.

Design requirement

The time width per UART sent by computer (baud rate 115200) is measured by logic analyzer.

Design and analysis

In the UART protocol, it is stipulated that the time width of each bit should be 1 second divided by the baud rate, but in the actual circuit, the two crystal oscillators with the same label will also have a certain error. We can use the logic analyzer (that is, using the FPGA clock) to measure the bit time width when PC sends UART.

Because the baud rate is 115200, 16-octave sampling is generally used in sampling. At this time, the sampling frequency is relatively high, and the clock of the basic 50MHz can not make an accurate 16-octave, which will bring some errors.

Using the logic analyzer, we can see that there are errors in both of the above, the deviation of the real sampling, and whether the deviation has an impact on our design.

Design and implementation

Make a copy of _ 9_uart_drive and name it _ 10_uart_drive_signal_tap. Then open the project and change the baud rate to 115200.

Click tools-> signal tap logic analyzer.

In the right window signal configuration, you first need to specify a sampling clock signal.

The logic analyzer samples data at each rising edge of the sampling clock. The logic analyzer does not support data sampling at the falling edge of the sampling clock. Any signal in the design can be used as a sampling clock. However, for the best data sampling results, use a global clock that is synchronized with the signal being tested.

In this design, all signals are driven by external clk signals, so the sampling clock is selected as clk. Click the three points at the back of the clock dialog box. Select filter as pin:all, click list, select clk in matching nodes, click "greater than", clk appears in nodes found, and then click ok.

After configuring the sampling clock signal, you need to configure the sampling depth.

For each signal in the sampled data, the sampling depth specifies the number of samples sampled and stored. In the case of limited device memory resources, the design may not be able to compile because the selected depth is too large. At this point, you need to reduce the sampling depth to reduce resource usage.

The sampling depth multiplied by the sampling interval determines the time width of the sampling. Now what we need to do is to sample a UART protocol frame, a protocol frame has 12 bit. According to the baud rate of 115200, the sampling time width should be 104166ns, so the sampling depth should be 5208, and the sampling depth should be 8K here.

When the sampling depth is determined, you can specify the amount of data sampled by the logic analyzer before and after the trigger event.

The logic analyzer offers three options. Pre indicates that 12% of the storage depth is used before the triggered event, 88% of the storage depth is used after the triggered event, Center indicates that 50% of the storage depth is used before the triggered event, 50% of the storage depth is used after the triggered event, and Post indicates that 88% of the storage depth is used before the triggered event and 12% of the storage depth is used after the triggered event.

Select Pre here.

After configuring this information, begin to add the signals that need to be observed.

In the setup interface, double-click in the blank interface to add the signal you want to observe.

The signals that need to be observed are uart_txd, uart_rxd and cap_cnt.

Uart_txd and uart_rxd are port signals. When you select filter, you can select PIN:all, cap_cnt as the internal signal, and signal tap: pre-synthesis when you select filter.

Set the falling edge of the uart_rxd as the trigger condition.

In the trigger conditions location of uart_rxd, right-click and select falling edge.

Click Save to save to qprj and name it stp1.stp.

Enable logic analyzer. Click Yes.

Go back to the quartus interface, conduct a comprehensive analysis and form a configuration file.

In the structure interface of the project wizard, you can see that two unknown components appear in the structure. These two are logic analyzers.

In the report, you can see an increase in the use of logical and memory resources.

Go back to the signal tap interface and connect the PC to the development board.

In hardware, select USB-blaster.

Click the three dots after sof manager, select the generated sof file, and then click download.

Click to run the analysis.

At this point, the logic analyzer is waiting to be triggered.

The trigger condition is the falling edge of uart_rxd, open the serial port assistant, and after configuration, send a data 11.

After sending, the waveform appears in the logic analyzer. Because the send is 11, the send data starts from the low bit, so the first data should be 1. Therefore, the low level at the first end is the starting bit, and its time width can be determined by the digital label of the sample.

The left button is to zoom in, and the right button is to zoom out.

The left side is 0 because the falling edge is used as the trigger condition. Zoom in on the number on the left to 434.

So the time width of the start bit is 434x20ns, or 8680ns. Calculated with a baud rate of 115200, the time width of each bit should be 8680.5556ns. This proves that the time width of the bit sent by PC is the same as we expected.

You can use this method to measure the width of other bit, some bit width is less than 8680ns, some bit width is more than 8680ns, but it is about the same.

Because the real width is different from what we think it is. But the design is that the width of each bit is an integral multiple of 20ns, so there will be a deviation when sampling. This can be seen by cap_cnt, and the longer the sampling, the greater the cumulative error.

At the first bit of the data, cap_cnt equals 7, which is about to become 8. According to the cap_cnt counting rule, the baud rate is designed to be 16 octave, so all subsequent bit should start with 16 * N + 7, and will soon become 16 * N + 8. But there is a certain deviation between the real time width and the expected time width.

At the beginning of the final parity-check bit, the cap_cnt data should be 135in terms of 16-octave sampling, and then quickly become 136. But by this time it is equal to 136, and immediately becomes 137.

We sample according to cap_cnt (sampling at the location where cap_cnt changes).

Because of the error, it is stipulated that the length of the protocol frame of UART cannot be too long. That is, the number of data bits in the middle can not be increased at will.

The figures of the above analysis steps are only the author's test results, and different PC and development board tests may get different results.

Summary of logic analyzer

The waveform running inside the development board can be viewed directly by using the logic analyzer. Therefore, in many cases, the logic analyzer is used for board-level testing as the final result.

If you do not need the logic analyzer in the project, you can open assignments-> settings-> signal tap logic analyzer, uncheck the enabled check box, and then recompile it.

The above is how to use the Signal tap logic analyzer. Have you learned the knowledge or skills? If you want to learn more skills or enrich your knowledge reserve, you are welcome to follow the industry information channel.

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