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This article introduces the relevant knowledge of "what is the status of cache line in Java". In the operation of actual cases, many people will encounter such a dilemma, so let the editor lead you to learn how to deal with these situations. I hope you can read it carefully and be able to achieve something!

Status of cache line:

1. Status M indicates that the data in the cache row has been modified and is inconsistent with the data in memory

2. Status E indicates that the data in the cache row has been modified and is consistent with the data in memory

3. Status S indicates that the data in the cache row is consistent with the data in memory and consistent with the cache line in other kernels

4. Status I indicates that the cache line is invalid

Each cache controller not only monitors the read and write operation of its own cache, but also monitors the read and write operation and state of other cache, so each cache line carries out state transition according to the current state and listening action, which is referred to as MESI consistency protocol. Read and write operations can be divided into four types (LR- kernel read this kernel read this kernel write book cache,RR- other kernels read their corresponding cache,RW- other kernels write their corresponding cache) the state transition process is as follows:

1. When the cache line where the data is in state I and LR occurs, if the data is not in other kernel cache line, the data is loaded from memory, and then the cache line state becomes E; if the data is in state M in other kernel cache line, it is written to memory and then the kernel is loaded from memory, and both cache line are in S state. If the data is in the other kernel cache line and is already in state S or E, this cache line is loaded from memory and becomes S state.

When the cache line where the data is in state I and LW occurs, the data is first loaded from memory and then modified in cache line, and the state becomes M; if the data is in other kernel cache line and the state is M, it is updated to memory and then the state is set to I; if the data is in other kernel cache line, and the state is E, the state is set to invalid I. The cache line state of this kernel has always been M.

There is no reaction when the cache line where the data resides is in state I and RR and RW are listening.

2. When the cache line where the data is located is in M state and LR occurs, it is read directly and the state remains unchanged.

When LW occurs, it is written directly and the state remains unchanged.

When the RR is monitored, the data is written to memory and the state changes to S.

When listening to the RW, the data is written to memory so that other memory can read the latest data, and then the status is set to invalid I.

3. When the cache line where the data is located is in the E state and LR occurs, it is read directly and the state remains unchanged.

When LW occurs, it is written directly and the state changes to M.

When the RR is monitored, the status changes to S.

When listening to RW, the status is set to invalid I.

4. When the cache line where the data is located is in S state and LR occurs, it is read directly and the state remains unchanged.

When LW occurs, the contents of cache line are modified and the state is changed to M, and the cache line of the rest of the kernel is set to invalid state I.

The state does not change when the RR is monitored.

When listening to RW, cache line sets invalid state I.

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