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This article mainly explains "how to use virtual interface". Friends who are interested might as well take a look. The method introduced in this paper is simple, fast and practical. Now let the editor take you to learn how to use virtual interface.

Interface encapsulates the module's port (ports), as well as their direction (modports), synchronization relationship (clocking block), function and task.

Interface simplifies the connection between modules, but it is not suitable for OOP-based test platform and cannot be instantiated in program and class.

To solve this problem, System Verilog introduced the concept of virtual interface. Virtual interface is the pointer to the actual interface. That is, virtual interface is a data type that can be instantiated in class, and virtual interface can be used to communicate indirectly with the design under test (DUT) without using hierarchical references.

Interface separates the test platform from DUT. Virtual interface manipulates a set of virtual signals at different locations of the test platform, rather than directly manipulating the actual signals.

Interface SBus; / / A Simple bus interfacelogic [7:0] addr, data;endinterface

Class SBusTransctor; / / SBus transactor class virtual SBus bus; / / virtual interface of type Sbus function new (virtual SBus s); bus= s; / / initialize the virtual interface endfunctionendclass

Module dev (Sbus s)... Endmodule / / devices that use SBus

Module topSBus s; / / instantiate interfacedev a (s); / / instantiate device

Initial beginSbusTransactor t; / / create bus-transactorst = new (s); endendmodule

In the previous example, SbusTransctor is a simple reusable transaction class that is written without knowing the hierarchy of the test platform or the specific design that interacts with it. This transaction class can interact with any number of designs that conform to the interface protocol.

When virtual interface is used in the test platform, the following three requirements need to be met

1. The instantiated interface must be correctly connected to the DUT.

SBus s; / / instantiate interfacedev a (s); / / instantiate device

2. The virtual interface handle must be declared in the class.

Virtual SBus bus; / / virtual interface oftype Sbusfunction new (virtual SBus s); bus = s; / / initialize the virtual interface endfunction

3. The interface of the specified module must be assigned to virtual interface

SbusTransactor t; / / create bus-transactorst = new (s)

UVM is a class-based validation method that requires access to DUT in two different locations, driver and monitor, so two virtual interface are required in UVM.

Setting up the virtual interface in UVM is as follows

Module top;... Dut_if dif;... Initial beginuvm_config_db# (virtual dut_if):: set (null, "*", "vif", dif); run_test (); endendmoduleclass tb_driver extends uvm_driver # (trans1); … Virtual dut_if vif;... Function void build_phase (uvm_phase phase); super.build_phase (phase); / / Get the virtual interface handle that was stored in the// uvm_config_db and assign it to the local vif field.if (! uvm_config_db# (virtual dut_if):: get (this, "", "vif", vif)) `uvm_fatal ("NOVIF", {"virtual interface must be set for:", get_full_name (), ".vif"}); endfunction... Endclass

The actual interface dif uses the command before run_test () in the top-level module

Uvm_config_db# (virtualdut_if):: set (null, "*", "vif", dif)

Stored in the (set) string "vif".

Then use the command

Uvm_config_db# (virtual dut_if):: get (this, "," vif ", vif)

From the same "vif" location and assign it to virtual interface vif in the tb_driver class.

At this point, I believe you have a deeper understanding of "how to use virtual interface". You might as well do it in practice. Here is the website, more related content can enter the relevant channels to inquire, follow us, continue to learn!

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