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What is SDRAM?

2025-01-21 Update From: SLTechnology News&Howtos shulou NAV: SLTechnology News&Howtos > Internet Technology >

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The main content of this article is to explain "what is SDRAM". Interested friends may wish to take a look. The method introduced in this paper is simple, fast and practical. Let's let the editor take you to learn what SDRAM is.

What is SDRAM?

Synchronous Dynamic Random Access Memory: synchronous dynamic random access memory. Synchronization: the soc sends the clock to the SDRAM, and the control signal is sent through the beat of the clock. Dynamic: memory needs to be constantly refreshed to ensure that data is not lost. Random: non-linear data storage, free to specify an address for data reading and writing

Internal and external structure of SDRAM

External

Fig. 1 this development board uses two pieces of sdram to configure sdram with 32bit bit width.

Inside

The retrieval principle of sdram is the same as that of a table. By specifying rows and then columns, you can accurately find the storage unit you need. However, due to technical / cost reasons, there can not be only one table in a sdram. At present, there are basically four tables. This table-like structure is called logical Bank, L-Bank. To find a storage unit, you have to determine which bank, then the row, and then the column.

Internal basic Operation and working time sequence of SDRAM

The row is valid

You must first enable the chip, select the corresponding L-BANK, then enable ROW, and then enable COLUMN to read and write to a memory cell.

Figure 2 Line effective sequence Chart

Select a L-BANK by BA0\ BA1, and distinguish rows from columns by RAS\ CAS. This happens at the same time, so row validity can also be called L-BANK efficiency.

Column reading and writing

After the row is selected, you can send the column address to read and write to the storage unit. Read / write commands are distinguished by WE signal lines, WE = 1: write; WE = 0: read

Figure 3 list of commands

As can be seen from the above table, all kinds of instructions in SDRAM are accomplished by the combination of high and low levels of control / address line, and there are no command words. So the read and write command is issued at the same time as the column address.

Fig. 4 schematic diagram of read and write operation

CAS (ColumnAddress Strobe, column address gating pulse) signal works with A0-A9/A11 (unfixed) to determine the specific column address.

Figure 5

When sending column read and write commands, there must be an interval with line valid commands, which is defined as tRCD, that is, RAS to CAS Delay (RAS to CAS delay), or line strobe period, which should be a delay based on the response time of electronic components in the chip storage array (the process of changing from one state to another). TRCD is an important timing parameter of SDRAM. The generalized tRCD is based on the number of clock cycles (tCK,Clock Time). For example, tRCD=2 represents a delay period of two clock cycles. When it comes to the exact time, it depends on the clock frequency. For the SDRAM,tRCD=2 of PC100, it represents the delay of 20ns, and for PC133, it is 15ns.

Analysis of each register configuration of S3C2440 storage controller

BWSCON = 0x2201 1110

BWSCON [31] = 0, disable data mask pins

Data mask

When talking about read / write operations, we talked about burst length. If BL=4, 4 × 64bit data is transmitted at a time. But what if the second piece of data is not needed? In order to shield the unwanted data, people use the Data I Mask O Mask (DQM) technology. With DQM, memory can control which output or input data is canceled by the Ithumb O port. It should be emphasized here that when reading, the masked data will still be transmitted from the memory bank, but will be masked at the "mask logical unit". To accurately mask each byte in a P-Bank bit width, each DIMM has eight DQM signal lines, each for one byte. In this way, for 4bit bit width chips, the two chips share a DQM signal line, for 8bit bit width chips, one chip occupies one DQM signal, and for 16bit bit width chips, two DQM pins are required. SDRAM officially stipulates that the DQM takes effect after two clock cycles are issued during read, while DQM is as effective as the write command when writing

BWSCON [30] = 0, disable WAIT signal

BWSCON [29:28] = 1 32bit; set the width of BANK7 data bus to 32bit

(BANK6 and BANK7)

BANKCONx = 0x0700

BANKCONx (0

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