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Editor to share with you what makefile refers to in linux, I believe most people do not know much about it, so share this article for your reference, I hope you can learn a lot after reading this article, let's go to know it!

In linux, makefile is the compilation rule of a project file, which describes the compilation and linking rules of the whole project, including which files need to be compiled, which files do not need to be compiled, which files need to be compiled first, which files need to be compiled after compilation, which files need to be rebuilt, and so on.

The operating environment of this tutorial: linux5.9.8 system, Dell G3 computer.

1. What is Makefile

Makefile can be simply thought of as a compilation rule of a project file, which describes the compilation and linking rules of the whole project.

For an enterprise project, there are usually many source files, sometimes in different directories according to functions, types and modules, and sometimes the source code of multiple programs is stored in one directory.

Makefle aims at the problem of how to compile some of the above code. It defines a set of rules that determine which files should be compiled first, which files should be compiled later, and which files should be recompiled.

What needs to be involved in compiling the whole project can be described in Makefile. In other words, Makefile can automate the compilation of our project projects without having to manually enter a bunch of source files and parameters every time.

The advantage of Makefile is that it can be compiled independently, and the whole project usually needs only one make command to complete compilation, linking, and even more complex functions. It can be said that any Linux source program comes with a Makefile file.

Advantages of 2.Makefile

Manage the compilation of the code, decide what files to compile, the compilation order, and whether recompilation is required

Save compilation time. If there are changes to the file, you only need to recompile the file instead of recompiling the entire project

Once and for all. Makefile usually only needs to be written once, and you don't have to change too much later.

3. Naming rules

Generally speaking, it is OK to name Makefile Makefile or makefile, but many source file names are lowercase, so more programmers use the name Makefile, because this can display Makefile first.

Naming Makefile to another name, such as Makefile_demo, is also allowed, but it should be used in the following ways:

Make-f Makefile_demo

4. Basic rules

The basic rules of Makefile are:

Goal: dependence

(tab) rules

Target-- > the target file to be generated

Rely on-- > generate some files needed for this goal

Rules-- > means of generating object files from dependent files

Tab-- > each rule must start with tab, not with spaces

For example, gcc test.c-o test, which we often write, can be written using Makefile as:

Test: test.c gcc test.c-o test

Where the test in the first line is the target, the test.c is the dependency, and the second line is the rule that the test is generated by test.c.

There are sometimes multiple goals in Makefile, but Makefile sets the first goal as the ultimate goal.

5. working principle

Generation of targets:

a. Check the existence of dependent files in the rule

b. If the dependent file does not exist, look for rules to generate the dependent file.

For example, in the figure above, the rule for generating calculator is gcc main.o add.o sub.o mul.o p.o-sub.o Makefil will first check whether main.o, add.o, sub.o, mul.o, p.o exist, and if not, it will look for rules to generate the dependent file.

For example, without the dependency of main.o, Makefile will look below to see if there are rules to generate main.o. When it finds that the rule gcc main.c-o main.o can generate main.o, it uses this rule to generate main.o, and then generates the ultimate target calculator.

The whole process is to look down for dependencies, and then execute the command up to generate the ultimate goal.

Updates to the target:

a. Check all dependencies of the target, and regenerate the target when any one of the dependencies is updated

b. If the target file is later than the dependent file, it needs to be updated.

For example, if the main.c is modified, the main.o target will be recompiled, and when the main.o is updated, the ultimate target calculator will also be recompiled. Updates to other files are also analogous.

6. Command execution

Make:

Use this command to generate the target file according to the predetermined rules.

If the name of the Makefile file is not Makefile or makefile, add the-f option, such as:

Make-f Makefile_demo

Make clean:

Clear the intermediate files (.o files) and the final target files generated during compilation.

If a file named clean exists in the current directory, the command is not executed.

-- > solution: pseudo-goal declaration: .PHONY:clean

Special symbols:

-: indicates that subsequent commands continue to be executed even if there is an error in the execution of this command. Such as:

-rm a.o build/

@: indicates that the command is only executed and is not echoed. When a general rule is executed, the executing rule will be printed on the terminal, and after this symbol is added, only the command will be executed and the executed rule will not be echoed. Such as:

@ echo $(SOURCE)

7. Ordinary variable

Variable definition and assignment:

Variables can be defined directly by assignment, such as:

INCLUDE =. / include/

Variable value:

Enclose in parentheses and add a dollar sign, such as:

FOO = $(OBJ)

The system comes with variables:

It's usually capitalized, such as CC,PWD,CFLAG, and so on.

Some have default values and some do not. For example, a few common ones:

CPPFLAGS: options required for preprocessors such as:-I

CFLAGS: the parameter used when compiling-Wall-g-c

LDFLAGS: options used by linked libraries-L-l

The default value of a variable can be modified. For example, the default value of CC is cc, but it can be changed to gcc:CC=gcc.

8. Automatic variable

Commonly used automatic variables:

Makefile provides many automatic variables, but the following three are commonly used. These automatic variables can only be used in commands in the rules, not anywhere else.

$@-- > goals in rules

$

The first dependency condition in the rule

$^-- > all dependency conditions in the rule

For example:

App: main.c func1.c fun2.c

Gcc $^-o $@

Where: $^ represents main.c func1.c fun2.c,$

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