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Why use latch in ICG Cell, many novices are not very clear about this, in order to help you solve this problem, the following small series will explain in detail for everyone, people who have this need can learn, I hope you can gain something.

Here is the simplest way to implement clock gating (using AND gates):

Theoretically, this is possible: when the enable signal Enable is high, the clock will be passed to the gated flip flop FF2.

The problem is timing. On the rising edge of the clock, the D input of flip flop FF1 propagates to the Q output, but the same rising edge of the clock also reaches the AND gate, which causes glitches in the gated clock.

Therefore, we use an integrated clock gating (ICG) cell that contains a low-level sensitive latch

When the clock is low, the input is allowed to propagate directly to the input of the AND gate. The clock is low, so the output of the AND gate will be low regardless of the enable input.

However, when the clock is high, the latch will close and prevent any change in the Enable value from propagating to the AND gate. This does not produce burrs.

When the clock goes low again, the latch reopens and the new enable value passes through the latch.

It is possible to build this type of circuit using separate gates (latch and AND gate), but this requires some additional timing checks in the synthesis/backend/STA.

Most ASIC libraries provide a standard ICG unit where timing has been described internally. Similar to flip flops and latches, the enable inputs of ICG cells also have setup and hold time requirements, which make timing analysis easy.

So why Latch-based ICG instead of Flip-Flop-based ICG?

If you use a rising-edge trigger, the same problem occurs as with the original clock gating design.

If a falling edge triggered flip flop is used instead of a low sensitive latch, the enable input is captured on the falling edge of the clock. The enable input of the AND gate remains stable until the next falling edge of the clock. Therefore, the burr problem is solved.

But this raises three questions:

A flip flop usually consists of two latches. As a result, Flip-Flop-based ICGs are twice as large as Latch-based ICGs.

Flip-Flop-based ICG increases power consumption compared to Latch-based ICG

Most importantly, the Flip-Flop-based ICG captures the enable input on the falling edge of the clock and must complete within half a clock cycle. While using a latch can take up the entire clock cycle (time borrow), because Latch is always able to propagate data at the active level, the flip flop can only propagate data at the edge.

Therefore, Latch-based ICGs have better power consumption, area, and timing than Flip-Flop-based ICGs.

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