Shulou(Shulou.com)06/02 Report--

one。 Introduction of pseudo-target

a. By default

1.make thinks the target corresponds to a file.

2.make compares the old and new relationships between the target file and the dependent file and decides whether to execute the command or not

3.make gives first priority to file processing.

Example

Hello.out all: func.o main.o gcc-o hello.out func.o main.ofunc.o: func.c gcc-ofunc.o-c func.cmain.o: main.c gcc-o main.o-c main.cclean: rm * .o hello.out

This example adds clean to the previous example

As you can see from the above figure, in the second we assume that there is a clean file in the directory (which can be created through the touch command). If we run make clean at this time, we will find that make always prompts that the clean file is up to date. Make behaves in principle because it treats clean as a file, because the file is found in the current directory, and the clean target does not have any prior conditions. So when make is asked to create a clean target for us, it assumes that clean is up-to-date and "refuses" to clean up the file.

This happens because our definition of clean goals is different from what make understands. It is inevitable that the target file name is duplicated with the target name in Makefile in real projects, so the concept of false target is put forward.

Pseudo-targets in makefile

1. Declare a pseudo target with the .PHONY keyword

two。 The false target does not correspond to any actual file.

3. Regardless of whether the dependency of the pseudo target is updated or not, the command is always executed

Pseudo-target syntax: declare first, then use

Add an example of .PHONY

.PHONY: cleanhello.out all: func.o main.o gcc-o hello.out func.o main.ofunc.o: func.c gcc-ofunc.o-c func.cmain.o: main.c gcc-o main.o-c main.cclean: rm * .o hello.out

The running result is shown in the figure

As shown in the figure, we can see that even if there is a clean file in the current directory, running the make clean command with a pseudo-target .PHONY will perform a delete operation.

two。 Different assignment methods and variables

Supporting the concept of variables in programming languages in 1.makefile

Variables in 2.makefile represent only text data (strings)

Variable name rules in 3.makefile

(variable names can contain characters, numbers, underscores; cannot contain ":", "#", "=" or ""; variable names are case-sensitive)

a. Definition and use of variables (you can make Makefile more maintainable by using variables)

.PHONY: cleanCC:=gccTARGET:=hello.out$ (TARGET): func.o main.o $(CC)-o $(TARGET) func.o main.ofunc.o: func.c $(CC)-ofunc.o-c func.cmain.o: main.c $(CC)-o main.o-c main.c.PHONY: rebuild clean allrebuild: clean allall: $(TARGET) clean: rm * .o $(TARGET)

The running result is shown in the figure.

You can see that after adding the variable, the result is the same.

The way variables are assigned in B.makefile

1. Simple assignment (: =)

two。 Recursive assignment (=)

3. Conditional assignment (? =)

4. Append assignment (+ =)

a. Simple assignment (: =)

1. General assignment method in programming language

two。 Valid only for variables of the current statement

.PHONY: allx=fooy=$ (x) bx=laterxx:=fooyy:=$ (xx) bixx:=laterall: @ echo "xx=$ (xx), yy=$ (yy)"

The result is as shown in the picture

b. Recursive assignment (=)

1. Assignment operations may affect multiple other variables

two。 All other variables related to the target variable will be affected

.PHONY: allfoo=$ (bar) bar=$ (ugh) ugh=MYLOVEall: @ echo $(foo)

The result is as shown in the picture

c. Conditional assignment (? =)

1. If the variable is not defined, define the variable using the value in the assignment symbol

two。 If the variable is already defined, the assignment is invalid

.PHONY: allx:=fooy:=$ (x) bx?=newall: @ echo "x = > $(x)" @ echo "y = > $(y)"

d. Append assignment (+ =)

1. Add a new value after the value of the original variable

two。 The original variable value is separated from the new value by a space

.PHONY: allx:=fooy:=$ (x) bx+= $(y) all: @ echo "x = > $(x)" @ echo "y = > $(y)"

three。 Use of predefined variables

1. Target @ is used to indicate the goal of a rule. When there are multiple targets in a rule, $@ refers to any of the targets that cause the rule command to be run.

2.$ ^ represents all the prerequisites in the rule

3.$ < indicates the first prerequisite in the rule

Use these rules to modify the previous code

CC: = g++TARGET: = hello.out$ (TARGET): func.o main.o $(CC)-o $@ $^ func.o: func.c $(CC)-o $@-c $^ main.o: main.c $(CC)-o $@-c $^ .PHONY: rebuild clean allrebuild: clean allall: $(TARGET) clean: $(RM) * .o $(TARGET)

The result is shown in the figure

The reason for this has been mentioned before to make Makefile more maintainable.

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