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This article mainly talks about "what is the relationship between SystemVerilog and UVM". Interested friends may wish to take a look. The method introduced in this paper is simple, fast and practical. Now let the editor take you to learn "what is the relationship between SystemVerilog and UVM"?

UVM provides a rich base class library and validation methodology, and is adopted by mainstream EDA tools, IP vendors, and design companies. Now, using SystemVerilog is basically the same as using UVM authentication.

If you want to ask me what is the relationship between SystemVerilog and UVM, I think the metaphor between Chinese characters and poetry may be more appropriate. Of course, I would not say that it is the relationship between code language and library. There is no room for imagination.

When the sky snows

SystemVerilog+UVM: all of a sudden, it's like a spring breeze blowing overnight, like thousands of trees and ten thousand pears in full bloom.

Only UVM:thousands of pear flowers bloom as if spring wind just passed by

Only SystemVerilog: "the scenery is picturesque and poems are given to the world. Why is there no culture? shit has a lot of snow."

SystemVerilog is a hardware design and verification language (hardware design and verification language,HDVL), an updated version of Verilog HDL.

In order to better support the verification environment, SystemVerilog provides the capabilities of object-oriented programming (OOP), constrained random incentives, assertions and functional coverage.

The main reason why verification platforms need to be based on UVM is: reuse

1. Reuse between tools

The SystemVerilog language reference manual has more than 1300 pages. There are differences in the implementation of mainstream EDA tools such as Cadence, Synopsys and Mentor, but they are consistent in supporting UVM, that is to say, UVM-based verification environments can be portable between different EDA tools.

2. Reuse between projects

The UVM-based verification environment is easy to reuse between projects, and it is easy for engineers to reach a consensus on the verification environment. This cannot be done using the SystemVerilog language alone.

3. Verify the reuse of IP

There are many standard protocols in SoC design, such as AMBA, DDR, Ethernet and so on. UVM can also facilitate the reuse and maintenance of VIP.

4. Reuse of solutions

Verification, like other software development, has the problems encountered by almost every project. UVM provides off-the-shelf solution implementation.

Here are some key concepts in UVM:

1 、 Components&Data

The classes in UVM fall into two main categories: Components and Data.

Components inherits from uvm_component,Data inherits from uvm_sequence_item.

Both uvm_component and uvm_sequence_item inherit from uvm_object.

Components is created at zero time (build_phase) before the simulation starts to consume time. After inheriting Components, the user can override the build_phase method.

Build_phase this kind of phase callback is top-down. You can see that the Components of UVM is a tree structure, and the root node has only one uvm_root (singleton object).

The Data generated in the simulation process flows through each Components like a data stream.

2. Factory mechanism

Using object-oriented programming technology, users can easily create new validation components based on base classes and manipulate user-defined objects in a general way using the inheritance feature of OOP. For example, error injection is performed on the basis of basic data transaction classes.

In order to make full use of the flexibility of this OOP in the verification platform, it is necessary to use the factory mechanism as a design pattern to replace classes in the verification process.

Class user_monitor extends uvm_monitor; `uvm_component_utils (user_monitor)...

3 、 configure&resourcedatabase

Configure can be seen as a globally accessible data resource that is retrieved using a string name. The corresponding verification platform can be configured according to the data value.

4 、 TLM connection

For components, instantiation needs to be completed in build_phase from top to bottom, and connections between components need to complete TLM connections in connect_phase from bottom to top, which are used for sending and receiving data streams.

At this point, I believe you have a deeper understanding of "what is the relationship between SystemVerilog and UVM". You might as well do it in practice. Here is the website, more related content can enter the relevant channels to inquire, follow us, continue to learn!

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