Shulou(Shulou.com)06/02 Report--

This article will explain in detail how the sharing and caching of Disruptor is, and the content of the article is of high quality, so the editor will share it for you as a reference. I hope you will have some understanding of the relevant knowledge after reading this article.

What is sharing?

The following figure shows the basic structure of the calculation. L1, L2 and L3 represent first-level cache, second-level cache and third-level cache, respectively. The closer to the CPU cache, the faster the speed and the smaller the capacity. So L1 cache is small but fast, and next to the CPU core that is using it; L2 is larger, slower, and still can only be used by a single CPU core; L3 is larger, slower, and shared by all CPU cores in a single slot; and finally, main memory, shared by all CPU cores in all slots.

Fig. 3 schematic diagram of computer CPU and cache

When CPU performs operations, it first goes to L1 to find the data it needs, then to L2, and then to L3. If none of these caches are in the end, the required data will go to the main memory. The farther you go, the longer the operation will take. So if you are doing something very frequently, you should try to make sure that the data is in the L1 cache.

In addition, when sharing a share of data between threads, one thread needs to write the data back to main memory, while another thread accesses the corresponding data in main memory.

The following is the concept of time for accessing different levels of data from CPU:

From CPU to approximately required CPU cycle takes about 60-80nsQPI bus transfer (between sockets, not drawn) about 20nsL3 cache about 40-45 cycles about 15nsL2 cache about 10 cycles about 3nsL1 cache about 3-4 cycles about 1ns register 1 cycle

It can be seen that CPU reading data from main memory will be nearly 2 orders of magnitude slower than reading from L1.

Cache Lin

Cache is made up of many cache line. Each cache line is usually 64 bytes, and it effectively refers to a block of addresses in main memory. The long type variable of a Java is 8 bytes, so eight variables of type long can be stored in a cache line.

Every time CPU pulls data from main memory, it stores adjacent data in the same cache line.

When accessing an long array, if one value in the array is loaded into the cache, it automatically loads another seven. So you can traverse this array very quickly. In fact, you can very quickly traverse any data structure allocated in contiguous memory blocks.

The following example is a test comparison between using the features of cache line and not using cache line.

Package com.meituan.FalseSharing; / * * @ author gongming * @ description * @ date 16-6-4 * / public class CacheLineEffect {/ / consider that the average cache line size is 64 bytes, with a long type of 8 bytes static long [] [] arr; public static void main (String [] args) {arr = new long [1024 * 1024] []; for (int I = 0; I < 1024 * 1024) For (int j = 0; j < 8; int +) {arr [I] [j] = 0L;}} long sum = 0L; long marked = System.currentTimeMillis (); for (int I = 0; I < 1024 * 1024; iTunes 1) {for (int j = 0; j < 8) Sum = arr [I] [j];}} System.out.println ("Loop times:" + (System.currentTimeMillis ()-marked) + "ms"); marked = System.currentTimeMillis (); for (int I = 0; I < 8; iTunes 1) {for (int j = 0; j < 1024 * 1024) Sum = arr [j] [I];}} System.out.println ("Loop times:" + (System.currentTimeMillis ()-marked) + "ms");}}

When tested in the running environment of 2G Hz, 2 cores and 8G memory, the speed difference is double.

Results: Loop times:30ms Loop times:65ms

What is pseudo sharing?

ArrayBlockingQueue has three member variables:-takeIndex: subscript of the element to be removed-putIndex: subscript of the location where the element can be inserted-count: the number of elements in the queue

These three variables are easy to put into a cache line, but there is not much correlation between modifications. Therefore, each modification will invalidate the previously cached data, so that the sharing effect can not be fully achieved.

Fig. 4 pseudo-sharing diagram of ArrayBlockingQueue

As shown in the figure above, when the producer thread put an element to ArrayBlockingQueue, the putIndex is modified so that the cache line in the consumer thread's cache is invalid and needs to be re-read from main memory.

This phenomenon of not making full use of the cache line feature is called pseudo-sharing.

For pseudo-sharing, the general solution is to increase the interval between array elements so that elements accessed by different threads are on different cache lines, trading space for time.

Package com.meituan.FalseSharing; public class FalseSharing implements Runnable {public final static long ITERATIONS = 500L * 1000L * 100L; private int arrayIndex = 0; private static ValuePadding [] longs; public FalseSharing (final int arrayIndex) {this.arrayIndex = arrayIndex;} public static void main (final String [] args) throws Exception {for (int itim1teri)

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