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How to carry out Makefile analysis, many novices are not very clear about this, in order to help you solve this problem, the following editor will explain for you in detail, people with this need can come to learn, I hope you can gain something.

What is Makefile?

Makefile is a script file needed by GNU-Make software, which can guide Make software to control arm-gcc and other tool chains to compile engineering files and finally get executable files. Almost all Linux distributions have built-in GNU-Make software, VScode and other IED also have built-in Make programs.

The xxx.mk files or Makefile you see are collectively referred to as Makefile script files.

Rules of Makefile

The rules of Makefile are as follows. Here [TAB] refers to the TAB key on the keyboard, not a space. If you enter a space before the command, it will cause an error, and the TAB key cannot be used arbitrarily in Makefile:

Goal: dependence

[TAB] command

For example:

Hello:

@ echo "Hello"

At this point, executing the make command will output a statement "Hello". The Hello is the target, and the dependency is empty. In order to generate the target, you need to execute the echo "Hello" statement, resulting in the output Hello.

For example, suppose we have a Hello.c C language source file that needs to be compiled and not linked to a Hello.o file, and finally linked. The Makefile content is as follows:

Hello.out: Hello.o

Gcc-o Hello.out Hello.o

Hello.o: Hello.c

Gcc-c-o Hello.o Hello.c

When the make command is executed, the make interpreter finds that the target is "Hello.out", but it needs Hello.o to generate Hello.out, finds that "Hello.o" cannot be found in the directory, looks down to see if there are rules for generating Hello.o, finds that "Hello.o" depends on "Hello.c", finds Hello.c in the directory, and executes the statement "gcc-c-o Hello.o Hello.c" to generate "Hello.o". As long as there are no errors in the compilation process, you can get "Hello.o", and then you can execute "gcc-o Hello.out Hello.o" to generate "Hello.out".

Where does the analysis begin?

Here can be used to analyze a C language or Java language program for analogy, generally based on the program is the execution flow to analyze, that is, the first to find the main function, because the main function is the program's execution entry, Makefile also has an execution entry, in the execution of make commands, make interpreter default search under the current directory named "Makefile" file, found, the execution of the first target generated by the command and generate its dependence on the command.

Here, select Makefile under the GCC directory of the STM32L431_BearPi project in the SDK/Targets directory to start the analysis.

Lines 1 through 140 set some variables and import some makefile files (there are no rules for setting variables). Line 143 is the first rule.

When we execute make or make all, we start to generate the all target, which depends on the TARGET (Huawei_LiteOS) .elf file in the BUILD_DIR (GCC/build) directory. BUILD_DIR and TARGET are two variables that are assigned at the beginning. As shown in the following figure, $(variable) is replaced with the value of the variable, for example, $(TARGET) .elf is eventually replaced with Huawei_LiteOS.elf.

However, Huawei_LiteOS.elf does not exist yet, so make has to continue to look down to see if there is a rule for generating Huawei_LiteOS.elf. Fortunately, the target of line 147 is Huawei_LiteOS.elf, which is the rule for generating Huawei_LiteOS.elf. The rule relies on three directories corresponding to $(OBJ_DIRS) $(C_OBJ) $(S_OBJ), which do not exist, so make has to continue to look down. It finds that line 152 happens to be the rule that targets the directory, creates the directory, solves the $(OBJ_DIRS) dependency, and then deals with the $(C_OBJ) dependency

Make looks down and finds the rule since the dependency was generated on line 156. Here, $(C_OBJ): $(BUILD_DIR) /% .o:% .c corresponds to the static mode in makefile. Let me briefly say that if you want to learn more, you can do it on your own.

The format of the static model is as follows:

Target list: models that match the target list: models that match dependencies

[TAB] command

Let's look at an example.

There are three values of foo.o, bar.o and test.s in the target list. First, find the model that matches% .o, and the test.s mismatch is abandoned. Replace the matching foo.o and bar.o with foo.c and bar.c. In the end, this rule is tantamount to enforcing the following two rules. Why do you do so? You can imagine the following, assuming that there are thousands of files in the target list, so that you can write a lot less rules:

Going back to the Makefile of LiteOS_Lab, line 156 regards the build/xxx.o-compliant file in the C_OBJ variable as a dependency on the xxx.c format, and the assignment of the C_OBJ variable is shown in the following figure:

The $(patsubst PATTERN, REPLACEMENT, TEXT) function is used to replace every word in TEXT separated by spaces (file name) that conforms to PATTERN format to REPLACEMENT format, such as line 124, replacing all file names in C_SOURCE variables with the .o suffix as long as they are in the SDK/ iot_link directory, and there is a file in the SDK/ iotlink directory that conforms to the model, link_main.c. When executing the command corresponding to this rule, the target file is link_main.o, lines 125 and 126 are the same as above.

Here we take link_main.c as an example to explain the instructions. After pattern replacement, the rules are as follows:

Link_main.o: link_main.c

$(CC)-c $(CFLAGS)-Wa,-a,-ad,-alms=$ (@:% .o =% .lst) $<-o $@

CC here refers to arm-none-eabi-gcc,CFLAGS, which refers to various compilation parameters. For example, the function of the-MMD-MP-Wno-missing-braces,$ (@:% .o =% .lst) function is to replace the value of the $@ target that matches the% .o model with%. Lst, here we replace link_main with link_main.o. Lst,$

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