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This article mainly explains "what are the two-state data types". Interested friends may wish to take a look. The method introduced in this paper is simple, fast and practical. Let's let Xiaobian take you to learn "what are the two-state data types"!

SystemVerilog adds many new data types to Verilog to improve memory utilization at runtime. The built-in data types of SystemVerilog can be divided into two-state data types and four-state data types. The two-state data type has only two states 0 and 1, while the four-state data type can have four states 0,1,X, and Z. Two-state data types consume less memory and emulate faster than four-state data types.

two-state data type:

bit: 1-bit two-state data type, which can be extended to multiple bits.

byte: 8-bit signed integer that can be used to store ASCII characters.

shortint: 16-bit signed integer.

int: 32-bit signed integer.

longint: 64-bit signed integer.

four-state data type:

logic

reg

wire

integer: 32-bit signed integer.

Time: 64-bit unsigned integer.

The integer type can be signed or unsigned, and the corresponding operation results are different. By default, byte, shortint, int, integer, and longint default to signed and bit, reg, logic, and wire default to unsigned.‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍

wire and reg

The wire data type is used to model hardware connections between circuit components. In other words, wire is similar to the real wire in the circuit.

The reg data type holds values of data until another value is placed on top of them. In other words, reg is like a register component.

integer, real and time

The integer variable can hold values from-2^31 to (2^31)-1.

The syntax for integer variable declarations is as follows:

integer integer_variable_name;

The real variable stores a 64-bit value. Real numbers can be specified in decimal notation (e.g., 14.72) or scientific notation (e.g., 39e8).

The syntax for real variable declarations is as follows:

real real_variable_name;

At the start of the simulation, both integer and real variables are initialized to zero.

integer a [0:64]; //an array of 65 integer values real float_v; //a variable that stores the real value time

Time stores a 64-bit unsigned integer that can be used with the $time system task to print simulation time.

The time data type does not support synthesis and can only be used for simulation.

The syntax for the time variable declaration is as follows:

time time_variable_name;

Parameters

Parameters represent constants, so it is illegal to modify the value of Parameters at runtime.

However, parameters can be modified at compile time to have different values than when the variable was declared. This allows us to customize module instances for different parameters.

The syntax for parameter variable declarations is as follows:

parametersize = 16 ;

logic

logic is an improved version of the reg variable from Verilog to SystemVerilog. In addition to being a variable, it can be assigned continuously, driven by doors and modules.

The syntax for logic variable declarations is as follows:

logic a, addr;

two-state variable

The two-state data type improves the performance and simulator memory usage of the four-state type. The two-state data types are bit, byte, int, shortint, longint, byte.

bit - Unsignedbyte, shortint, int, longint - Signed

unsigned two-state types,bit single_bit ; // unsigned single bitbit [31:0] 32_bit ; // 32-bit unsigned integer

signed two-state types,int integer ; // 32-bit signed integerbyte 8_bit ; // 8-bit signed integershortint 16_bit ; // 16-bit signed integerlongint 64_bit ; // 64-bitsigned integer

unsigned from signedtwo-state types,int unsigned integer ; // 32-bit unsigned integerbyte unsigned 8_bit ; // 8-bit unsigned integershortint unsigned 16_bit ; // 16-bit unsigned integerlongint unsigned 64_bit ; // 64-bit unsigned integer At this point, I believe that everyone has a deeper understanding of "what are the two-state data types". Let's actually operate it! Here is the website, more related content can enter the relevant channels for inquiry, pay attention to us, continue to learn!

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