Shulou(Shulou.com)06/01 Report--

In this issue, the editor will bring you about how CPU accesses memory. The article is rich in content and analyzes and narrates it from a professional point of view. I hope you can get something after reading this article.

Memory management can be said to be a relatively difficult module to learn, the reason why it is more difficult to learn. First, memory management involves the implementation principle of hardware and complex algorithms of software, and second, there are too many wrong explanations about memory management on the Internet. Hope to do a series of memory management, from the hardware implementation to the underlying memory allocation algorithm, and then from the kernel allocation algorithm to the application memory partition, to how to interact with the hard disk and so on, to thoroughly understand the whole framework of memory management. The following is mainly about hardware principles and paging management.

CPU accesses memory through MMU

Let's look at a picture first:

From the figure, you can clearly see how CPU, MMU, and DDR are distributed in hardware. First of all, when CPU accesses memory, it needs to convert virtual address to physical address through MMU, and then access memory through bus. After MMU is enabled, all the addresses seen by CPU are virtual addresses. After CPU sends this virtual address to MMU, MMU will find out what the physical address corresponding to the virtual address is in the page table through the page table, and then access the outside DDR (memory stick).

So if you understand how MMU converts virtual addresses into physical addresses, you can understand how CPU accesses memory through MMU.

MMU converts virtual address to physical address through page table. Page table is a special data structure, which stores the corresponding relationship between logical page and physical page frame in the page table area of system space. Each process has its own page table.

The virtual address accessed by CPU can be divided into: P (page number), which is used as the index of the page table; d (page offset), the address offset within the page. Now let's assume that the size of each page is 4KB, and the page table has only one level, then the page table looks like this (each row of the page table is 32 bit, the first 20 bit represents page number p, and the last 12 bit indicates page offset d):

The relationship between CPU, virtual address, page table and physical address is shown in the following figure:

The page table contains the base address of the physical memory in which each page is located, which is combined with the page offset to form a physical address, which can be sent to the physical unit.

Above, we found that if you use a first-level page table, each process needs a 4MB page table (if the virtual address space is 32 bits (that is, 4GB), each page maps 4KB, and each page table item accounts for 4B, then the process needs 1m page table entries (4GB / 4KB = 1m), that is, the page table (each process has a page table) takes up the memory space of 4MB (1m * 4B = 4MB). However, for most programs, the space they use is far from 4GB, so why map the space that is impossible to use? In other words, the first-level page table covers the entire 4GB virtual address space, but if the page table entry of a first-level page table is not used, there is no need to create a second-level page table corresponding to this page table entry, that is, you can create a second-level page table only when needed. To do a simple calculation, assuming that only 20% of the first-level page table items are used, then the page table occupies only 0.804MB (1K * 4B + 0.2K * 1K * 4B = 0.804MB). In addition to creating a second-level page table when needed, you can also transfer this page from disk to memory, only one level page table is in memory, only one second-level page table is in memory, and the rest are all in disk (although this is very inefficient), then the page table takes up 8KB (1K * 4B + 1 * 1K * 4B = 8KB), and the space is reduced many times compared to the 0.804MB in the previous step! All in all, using multi-level page tables can save memory.

The second-level page table is to repage the page table. Still taking the previous 32-bit system as an example, a logical address is divided into 20-bit page numbers and 12-bit page offset d. Because the page table is to be re-paged, the page number can be divided into 10-digit page number p1 and 10-bit page offset p2. Where p1 is used to access the index of the external page table, and p2 is the page offset of the external page table.

This is how CPU accesses memory shared by the editor. If you happen to have similar doubts, you might as well refer to the above analysis to understand. If you want to know more about it, you are welcome to follow the industry information channel.

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