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This article mainly explains "what the arm9 interrupt structure is like". The content in the article is simple and clear, and it is easy to learn and understand. Please follow the editor's train of thought to study and learn how the arm9 interrupt structure is.

Interrupts in S3C2440 can be divided into two categories: external interrupts and internal interrupts.

An external interrupt

EXTINT [x]: used to configure the interrupt trigger mode of each pin (high level trigger, low level trigger, falling edge trigger, rising edge trigger). Note the corresponding relationship between the register and the interrupt source.

EINTPEND [x]: the registers of xxxPEND are all status registers. Clear the flag when initializing, and assign the value of the register to itself when clearing the interrupt.

EINTMSK [x]: 1 masked interrupt; 0 unmasked

SRCPEND [x]: 1 apply for interruption; 0 not apply for interruption

EINTFLT0~EINTFLT3: configure filter clock and filter width

INTMOD [x]: 1: FIQ, 0: IRQ

2. Internal interrupt

There are two kinds of internal interrupts: tape interrupts and non-tape interrupts.

No tape interruption: SRCPEND is set after the interruption occurs. If it is not blocked by INTMSK, then continue to apply for interruption in the next step.

Tape interruption: after the interruption occurs, set the SUBSRCPEND first, and apply to SRCPEND for interruption if there is no INTSUBMSK shield. If it is not blocked by INTMSK, further request for interruption.

Priority of interrupt:

ARB_MODEx: controls whether the interrupt priority is rotated

ARB_SELx: control rotation order

Turn on interrupt (xxxMSK):

1 external interrupt: EINT4~23 initializes EINTMSK and INTMSK first, and initializes INTMSK directly if it is EINT0~3

2 Internal interrupt: initialize INTSUBMSK first and then initialize INTMSK with sub-interrupt, and initialize INTMSK directly if it is an internal interrupt without sub-interrupt

Removal of interrupts (xxxPEND):

1 external interrupt: if EINT4~23 clears EINTPEND first and then INTPEND (note the sequence), if EINT0~3 clears SRCPEND directly. (no need to clear INTPEND???)

2 Internal interrupt: if the tape is interrupted, clear SUBSRCPEND first and then clear SRCPEND (pay attention to the sequence); clear SRCPEND directly without tape interruption

3 clear interrupt is write 1 clear

Three code parsing @ * * @ File:head.S@ function: initialize, set the stack of interrupt mode and management mode Set up the interrupt handling function @ *. Extern main.text.global _ start_start:@* * * @ interrupt vector In this program, except for Reset and HandleIRQ None of the other exceptions use @ * b Reset@ 0x04: vector address of undefined instruction abort mode HandleUndef: B HandleUndef@ 0x08: vector address of administrative mode Enter this mode through SWI instruction HandleSWI: B HandleSWI@ 0x0c: vector address of exception caused by instruction prefetch termination HandlePrefetchAbort: B HandlePrefetchAbort@ 0x10: vector address of exception caused by termination of data access HandleDataAbort: B HandleDataAbort@ 0x14: reserved HandleNotUsed: B HandleNotUsed@ 0x18: vector address of interrupt mode note that b HandleIRQ@ 0x1c is implemented here: Fast interrupt mode vector address HandleFIQ: B HandleFIQReset: ldr sp = 4096 @ set stack pointer The following are all C functions. You need to set the stack bl disable_watch_dog @ to close WATCHDOG before calling. Otherwise, CPU will continue to restart msr cpsr_c, # 0xd2 @ enters break mode ldr sp, = 3072 @ sets interrupt mode stack pointer msr cpsr_c, # 0xd3 @ enters management mode, and reset is followed by management mode, so the setting here and ldr sp under reset, = 4096, have the same effect. Ldr sp can be omitted in this code. = 4096 @ set the management mode stack pointer @ in fact, after the reset, CPU is in administrative mode. The "ldr sp, = 4096" before @ completes the same function. This sentence can be omitted from bl init_led @ initializing LED's GPIO pin bl init_irq @ to call the interrupt initialization function. Set I-bit=0 in msr cpsr_c, # 0x5f @ in init.c Turn on the IRQ interrupt ldr lr, = halt_loop @ set the return address ldr pc, = main @ call the main function halt_loop: B halt_loopHandleIRQ: sub lr, lr, # 4 @ calculate the return address stmdb spares, {r0merr12 L r} @ save the used register @ Note At this time, sp is the sp @ initial value of the break mode is 3072 ldr lr set above, = int_return @ sets the return address ldr pc after calling ISR, that is, the EINT_Handle function, = EINT_Handle @ calls the interrupt service function. In interrupt.c, int_return: ldmia spares, {r0lyr12 ~ ~ PC} ^ @ is returned after interruption. ^ means copying the value of spsr to cpsr.

Note: 1. Here interrupts are determined not by name, but by the address of the interrupt vector (0x0 / 0x4 / 0x8 / 0xc / 0x10.). IRQ is exactly 0x18. You only need to place a jump instruction in this location to interrupt isr. This means that any IRQ has to enter the interrupt through this entry, and then check which source applied for the interrupt.

The chip uses different sp and lr registers in each mode, and reset is followed by the management mode, so the ldr sp of the management mode, = 4096, is equivalent to the sp statement under reset.

/ / init.c: initialize LED and interrupt # include "s3c24xx.h" / / LED1,LED2,LED4 corresponds to GPF4, GPF5, GPF6#define GPF4_out (1

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