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This article mainly shows you the "sample analysis of the interruption of the STM32 network", which is easy to understand and clear. I hope it can help you solve your doubts. Let the editor lead you to study and study the "sample analysis of the interruption of the STM32 network".

01. Introduction

Network interrupt vector: one for normal network operation and the other for Ethernet wake-up events (with wake-up frames or magic packet detection) when it is mapped to EXIT line 19

The first network outage is reserved for interrupts generated by MAC and DMA, as in the MAC and DMA interrupts.

The second interrupt is reserved for the interrupt generated by the PMT during the wake-up event. The mapping of the wake-up event to the EXIT line 19 causes the STM32F20X and STM32F21X to exit the low-power mode and generate interruptions.

When an Ethernet wake-up event mapped to the EXIT line 19 occurs, the MACPMT interrupt enables and the EXIT line 19 interrupt with a rising edge is also enabled, and they are all able to wake up the interrupt.

The watchdog timer (see ETH_DMARSWTR register) can be used to flexibly control RS bits (ETH_DMASR register). When the watchdog timer is programmed with a non-zero value, the watchdog timer is activated, as long as the RXDMA finishes sending a received data frame to the system storage, the receive state is not triggered, because it is not enabled in the corresponding receive descriptor (RDES1 [31]) (i.e., not in the corresponding receive descriptor (RDES1 [31]) enable receive state). When the timer runs according to the programming value, the RS bit is set to 1 and an interrupt occurs if the corresponding bit in the ETH_DMAIER register is enabled. Watchdog timing expires before running, when the data frame is sent to memory, and RS is set to 1 because the timer is enabled to be a descriptor.

Note:

Reading the PMT control and status register automatically clears the received wake-up frame and the received magic packet PMT interrupt flag. However, because the registers used for these flags are in the CLK_ RX domain, there may be a significant delay before the firmware can detect this update. This delay can be particularly long when the RX clock is slow (in 10 Mbit mode) and when the AHB bus is high.

Because the interrupt request from PMT to CPU is based on the same register in the CLK_RX domain, CPU may mistakenly call the interrupt routine a second time even after reading the PMT_CSR. Therefore, firmware may be required to poll received wake-up frames and received magic packet bits and exit the interrupt service program only if they are found to be'0'.

02, Code

In fact, the network interruption of STM32 should be the interruption of the network-specific DMA. The packets in the network conform to the 1518 rule, that is to say, 1460 bytes, and the data packets received by MAC are 2K bytes. Every packet on the network will be interrupted after it is received by MAC.

The official code is like this.

It is obvious that the query is used, without interruptions.

Interrupts are used in the following ways:

Configure network outage

Comment out the code of the query section provided by the government.

After we use the interrupt form, the code is

With this kind of code, we have no problem receiving data smaller than a DMA descriptor data size, and it is very smooth.

Errors will occur when receiving a large amount of data, the reception will be slow, and too much will crash.

The solution is:

Change if to while

This solves the problem by receiving the entire packet and then jumping out of the interrupt.

The above is all the contents of the article "sample Analysis of STM32 Network outages". Thank you for reading! I believe we all have a certain understanding, hope to share the content to help you, if you want to learn more knowledge, welcome to follow the industry information channel!

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