Shulou(Shulou.com)06/02 Report--

one。 Examples of variables and functions

Requirements for exampl

1. Automatically generate target folders to hold executable files

two。 Automatically generate objs folder to store the object files generated by compilation

3. Compile options that support debug versions

4. Consider the extensibility of the code

Required to complete the example

1.$ (wildcardpattern) gets the list of files or directories in the current working directory that meet pattern

2.$ (addprefix,_name) adds the prefix _ prefix to each name in the name list name

Key skills

1. Automatically get the list of source files in the current directory (function call)

SRC: = $(wildcard * .c)

two。 Generate a list of target files based on the list of source files (value substitution of variables)

OBJS: = $(SRCS:.c=.o)

3. Prefix the path to each list of target files (function calls)

OBJS: = $(addprefix path/,$ (OBJS))

Pattern substitution in rules (directory structure)

Dependency of compilation rules

Compiled sample code and run result

CC: = gccMKDIR: = mkdirRM: = rm-frDIR_OBJS: = objsDIR_TARGET: = targetDIRS: = $(DIR_OBJS) $(DIR_TARGET) TARGET: = $(DIR_TARGET) / hello-makefile.out# main.c const.c func.cSRCS: = $(wildcard * .c) # main.o const.o func.oOBJS: = $(SRCS:.c=.o) # objs/main.o objs/const.o objs/func.oOBJS: = $(addprefix $(DIR_OBJS) / $(OBJS)). PHONY: rebuild clean all$ (TARGET): $(DIRS) $(OBJS) $(CC)-o $@ $(OBJS) @ echo "Target File = > $@" (DIRS): $(MKDIR) $@ $(DIR_OBJS) /%. C ifeq ($(DEBUG)) True) $(CC)-o $@-g-c $^ else $(CC)-o $@-c $^ endifrebuild: clean allall: $(TARGET) clean: $(RM) $(DIRS)

Running result

Summary:

1. Directories can become dependencies on targets, creating directories in rules

two。 Predefined functions are an indispensable part of makefile

3. The pattern matching here can be directly targeted at the files in the directory.

4. Special target versions can be compiled using command line variables

two。 Automatically generate dependencies

one。 Defects caused by compilation behavior

1. The preprocessor inserts the code in the header file directly into the source file

two。 The compiler can only generate the target file from the preprocessed source file.

Therefore, depending on the source file in the rule, the command may not be executed

Example

In the first picture, you can see that main.c and func.c are dependent on func.h. The result of running after changing the print information in func.h is shown below.

From the running results, you can see that the printed information has been changed, but the result after make has not changed. This is because it does not depend on the func.h operator, so after its printed information has changed, the result remains the same. The following modifications are needed to modify the printed information, and the running result is also changed (as shown in the figure).

It can be concluded from the above solution

1. The header file appears as a dependency bar in the rules corresponding to each target

two。 When the header file changes, any source file will be recompiled

3. When there are a large number of header files in the project, makefile will be difficult to maintain

two。 Improved method

1. Automatically generate dependencies on header files through commands

two。 Automatically include generated dependencies in makefile

3. Automatically confirm the files that need to be recompiled when the header file changes

Required conditions

1.Linux Command sed

two。 The compiler relies on the generation option gcc-MM (gcc-M)

Sed command in A.Linux

1.sed is a stream editor for modifying streaming text (add / delete / check / modify)

2.sed can be used for string substitution in streaming text

The string substitution method of 3.sed is: sed's _ RCC _ des_ g'.

B.sed 's regular expression support

1. In sed, you can replace the target with an expression matching.

two。 And the matching target can be used to generate replacement results.

C.gcc key compilation options (generate dependencies)

1. Get the full dependency of the target (gcc-M test.c)

two。 Get the partial dependency of the target (gcc-MM test.c)

Include keyword in D.makefile

1. Similar to include in C language

two。 Move the contents of other files into the current file intact

The way make handles include keywords

a. Search for target files in the current directory or in a specified directory

1. Search successful: move the file into the current makefile

two。 Search failed: generate warning

a. Find and execute corresponding rules with the file name as the target

b. If the rule corresponding to the current file name does not exist, an error is eventually generated.

Code example and running result

The execution Mechanism of commands in makefile

1. Each command in the rule is executed in a new process by default

two。 You can combine multiple commands into a single command through the concatenation character (;).

3. The combined commands are executed in the same process in turn.

4.set-e specifies to exit execution immediately after an error occurs

Example:

The main purpose of this code is to create a new test folder under the current folder, then enter the test folder and create a subtest folder, but the result after make is shown in the figure. You can see that subtest and test folder are in the same level directory, which is not the result we want.

The modified code and the running result

three。 Comprehensive example

Idea: get .dep dependent files through gcc-MM and sed, and include all .dep dependent files through the inclue instruction.

The result of the operation:

The problem that may arise in this example is how to organize .dep files to a specified directory in makefile

The way to solve it:

When include discovers that the .dep file does not exist:

1. Create deps files through rules and commands

two。 Create all .dep files to the deps folder

The 3..dep file records the dependencies of the target file

Code implementation

Summary:

a. Using the minus sign (-) turns off not only warnings issued by include, but also errors, which make ignores when they occur

b. When the target file does not exist (find the rule by file name and execute it)

c. When the target file does not exist and the found rules create the target file (include the successfully created object file in the current makefile)

d. When the target file exists (include the target file in the current makefile and find out whether there are corresponding rules with the target file name)

e. When the target file exists and the rule corresponding to the target name is executed (the command in the rule updates the target file, make re-includes the target file, replacing the previous contents), the target file is not updated (no action)

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