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What this article shares to you is about how to implement the FPGA of IIC protocol. The editor thinks it is very practical, so I share it with you to learn. I hope you can get something after reading this article.

FPGA implementation of IIC Protocol

  figure 1 13 modeling diagram of IIC module

   figure 1 13 is the modeling diagram of the IIC storage module. On the left is the top signal, and on the right is the question and answer signal for communication. Write address iAddr, write data iData, and read data oData. There are two characters in Call/Done, which means that the module has read function and some functions. Let's take a look at the code for details:

  Code 2 1 IIC Code statement

1. Parameter FCLK = 10'd125, FHALF = 10'd62, FQUARTER = 10'd31

2. Parameter THIGH = 10'd30, TLOW = 10'd65, TR = 10'd15, TF = 10'd15

3. Parameter THD_STA = 10'd30, TSU_STA = 10'd30, TSU_STO = 10'd30

   is shown in Code 21. FCLK represents the period of 400Khz, FHALF represents 1 cycle, and FQUARTER represents 1 cycle.

  figure 2 14 starting bit

  , first of all, let's take a look at the jigsaw puzzle from the beginning. As shown in figure 214, the left is the ideal timing of the starting bit, and the right is the physical timing of the starting bit. The starting bit of IIC bus is similar to that of serial port or PS/2, but the difference is that the starting bit of IIC bus is that SCL pulls up TR + TSU_STA + THD_STA + TF for a long time, while SDA pulls up TR + THIGH and then lowers TF + TLOW. The time taken by the sum of the starting bits happens to have a period of rate. This can be described by Verilog, and the result is as follows:

  code 22 IIC start bit generation code

1. Begin

2. IsQ = 1

3. RSCL

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