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2025-01-22 Update From: SLTechnology News&Howtos shulou NAV: SLTechnology News&Howtos > Servers >
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RISC-V architecture instruction set and privilege mode is what, many novices are not very clear about this, in order to help you solve this problem, the following small series will explain in detail for everyone, there are people who need this can learn, I hope you can harvest.
Since the RISC-V project started in 2010, it has been 10 years. The RISC-V Foundation has approved the RISC-V Base ISA, Privileged Architecture, Processor Trace and other specifications. RISC-V's basic support for Linux has also been completed. This article attempts to explain RISC-V's basic support for Linux, including instruction sets and exception handling, in an easy-to-understand way. Memory management, migration to RISC-V, UEFI, KVM and other support, welcome to continue to pay attention to this public number.
ISA
Seeing is believing, here is RISC-V assembly language. Disassembled from the author's code, the function is to output the incoming character c to the terminal through the standard interface provided by RISC-V (here referred to as OpenSBI, see below).
RISC-V instruction set specification
To do a good job in an ecosystem, we need to align our goals. RISC-V specifications (see link 1) play such a role. The current specifications are divided into two parts. Volume 1 is non-privileged instructions and Volume 2 is privileged instructions. In Volume 1, RISC-V defined two basic integer operations, RV32I and RV64I, with the following extensions.
Now the problem comes, so many specifications, if everyone uses inconsistent instruction sets, isn't it impossible to interoperate? Don't worry, RISC-V also defines the following combination of instruction sets.
In order to increase instruction density and save memory space, RISC-V also has the above-mentioned C extension (compressed instructions), for example, RV32GC indicates the RV 32G instruction set using compressed instructions, and RV64GC indicates the RV 64G instruction set using compressed instructions. According to Andrew Waterman's test, in Spec2006(a commercial test suite for CPU performance), the RV32GC and RV64GC save 30%+ space over the RV32G and RV64G, respectively, with little change in performance, see Reference 2.
In addition to non-privileged instructions, RISC-V specifications include privileged instructions. Privileged Spec Machine ISA and Supervisor ISA have been released in version 1.11. Virtualization ISA is currently 0.6 and is still under discussion.
ISA Brief
Understanding the instruction set helps us understand this architecture. RISC-V is a RISC architecture. All operations are performed between registers, with separate load and store instructions reading data from and writing data back to memory. In terms of overall instruction set architecture, the team led by Professor Bao Yungang has done a good Chinese translation (refer to Link 3). I will not elaborate on it here, just give two examples
"Addi sp,sp,-32" is to subtract 32 from the sp register and save it to the sp register. This instruction prepares the stack space for this function.
"Sd ra,24(sp)" is to save this return address (ra) on the stack, 24(sp) indicates the position relative to +24, which is defined by RISC-V binary call specification.
pseudoassembly
When reading code at ordinary times, in addition to the assembly instructions defined in the architecture, pseudo-assembly will also be encountered. Pseudo-assembly is something that helps us improve the efficiency of our usual handwritten assembly. For example, register assignment, the following li pseudo-instruction will be translated into lui and addiw instructions.
As another example, csrw is used to write to the csr register. The full name of csr is Control and Status Register, which is mainly related to privilege management.
exception handling
Knowing the basic assembly language allows us to learn more about RISC-V exceptions, which is one of the responsibilities of the operating system (another important responsibility is virtual memory management, described in the next article).
For ease of understanding, let's compare it to ARM and X86.
About 40 years ago, x86 architecture had the protection pattern shown above. Level0 runs the operating system and Level3 runs applications. To support virtualization, x86 introduces VMX operation(shown below), Guest operating systems and applications run in non-root mode, and hypervisors run in root mode. With this design, it is convenient to support both Type-1 and Type-2 virtual machine technologies, and the original operating system can run as a Guest operating system without any modifications. However, early x86 virtualization also had drawbacks, such as not supporting secondary page table conversion and requiring shadow page tables, which was inefficient until the introduction of EPT to solve this problem.
ARM architecture, by contrast, takes a different approach. Because ARM architecture already has the following Normal and Secure world design (here refers to the Normal world operating system, such as Linux, can run in Secure world without modification). There is no x86-like VMX root and non-root operations added.
Instead, a new exception level EL2 (Hypervisor) is added as shown below, which is easy to understand because EL2 has more levels than EL1. The problem is that EL2 is not a copy of EL1, meaning the Linux kernel cannot run directly on EL2. For Xen, a typical Type-1 virtualization mechanism, there is no problem. Xen hypervisor can run happily on EL2. KVM, as a module of the Linux kernel, is awkward: KVM requires some permissions from EL2, but Linux can only run on EL1. As a result, KVM, which was originally complete on x86, was split into high-visor and low-visor(parts requiring EL2 privileges). KVM's high-visor is usually happy to run with the Linux kernel in EL1, but when privileged operations for virtualization management are required, KVM falls from high-visor to low-visor processing.
ARM virtualization technology is many years later than x86, one advantage is that it can complete the state obtained by multiple iterations of x86, such as the EPT introduced by x86 to avoid shadow page table mentioned above, which is natively supported when ARM virtualization is extended. Meanwhile, ARM virtualization extensions are exactly the same for both 32-bit and 64-bit architectures, and early virtualization efforts, both xen and KVM, were done on Cortex-A15 and Cortex-A7 for the 32-bit ARMV7a architecture. After ARM64 was launched, virtualization did not need to be redone. As for the performance problems caused by more exception handling on ARM virtualization, starting with ARM v8.1, there is VHE mode, which supports sinking EL1 to EL2 operation, so that KVM ARM does not have the overhead mentioned above.
From the above history, it can be seen that the synergy of software and hardware, flexible and scalable design is very important. This is also reflected in the RISC-V design. RISC-V supports up to three privilege levels without virtualization features. Generally, in order to support a Rich OS like Linux, you need to support all three modes. Each level has different permissions. Bootloader/BIOS/UEFI runs the highest level of the system in machine mode, Linux kernel runs in supervisor mode, and applications run in user mode. By default, all exceptions are handled in machine mode. With the Linux kernel, this significantly reduces efficiency: all exceptions that could otherwise be handled by the Linux kernel, such as missing pages for applications, need to be dropped into machine mode before being forwarded to the kernel. To allow software systems to manage exceptions more flexibly, RISC-V introduces delegation, which allows the hardware to pass some exceptions and interrupts directly to the kernel in supervisor mode.
Now the question arises, how was RISC-V virtualization designed? Obviously, the privilege level of virtualization requires support for a Rich OS like the Linux kernel. So RISC-V doesn't add virtualization exceptions directly between supervisor mode and machine mode like early ARM virtualization, but defines a separate virtualization mode, which is combined with user and supervisor mode, resulting in the following table.
(Table from The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Document Version 1.12-draft Table 5.1)
This is a bit abstract and is illustrated by Anup Patel, one of the authors of RISC-V kVM (photo courtesy of the author, see link 4 for the original).
Note: The RISC-V virtualization specification is currently in draft 0.6, and there may be minor changes in the future.
SBI
Knowing RISC-V's privileged mode, what specifications do different levels of software calls follow? In RISC-V design, the lower layer (hardware/software) is transparent to the upper layer, the specification defines the binary interface, and there is no requirement on how to implement it. For example, when the Linux kernel is in supervisor mode, the following privilege levels are accessed through SBI(Supervisor Binary Interface). The software accessed by SBI is called SEE(Supervisor Execution Environment). SEE can be bootloader, BIOS, or Hypervisor. Similar to SEE is AEE, the runtime environment that supports applications.
(Image from The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Document Version 1.12-draft Figure 1.1)
See Reference Link 5 for SBI specifications, which define SBI capabilities such as obtaining a version of SBI specifications, sending or receiving a character, remote fence, setting timer, sending IPI interrupts, managing RISC-V processors (called hart in RISC-V), etc., as well as SBI binary call specifications. As of this article, SBI is 0.3 draft, this version mainly adds SBI interface for system reset. Since SBI is a specification, there are various implementations, and OpenSBI is one of them, which supports generic(RISC-V virt machine supporting qemu), sifive and k210 chips.
That's a bit abstract, so let's take a simple example. If you want to write a simple code that calls SBI interface to print characters from supervisor mode, how do you do it?
First, assuming that we have a C runtime environment, we need to pass the specified extension ID using register a7 according to the binary call specification defined by SBI.
(Image from RISC-V Supervisor Binary Interface Specification Version 0.3-rc0 p6)
As you can see from the diagram below, the extension ID is 1. We also see that the function prototype is passed the character ch as the first argument.
(Image from RISC-V Supervisor Binary Interface Specification Version 0.3-rc0 p6)
Which register does RISC-V use to store the first parameter? According to RISC-V ELF psABI
The integer register calling convention for specification (see link 6 ), we can see that register a0 is used to pass the first parameter. The code for sending a character looks like this.
Write SBI call interface, not everything is fine, if you want bootloader to load our code directly, we also need to prepare our own c language runtime environment. Add the following compilation lines.
cpu_enter will print the string. We chose to load our binary from fixed 0x80200000 using OpenSBI's fw_jump, the boot effect is as follows. The last line "Hello XU Xiake" is printed in the code above. I hope we can explore RISC-V's various features by writing code like Xu Xiake.
Did reading the above help you? If you still want to have further understanding of related knowledge or read more related articles, please pay attention to the industry information channel, thank you for your support.
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