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This article mainly explains "what is the content of the linux makefile file", interested friends may wish to have a look. The method introduced in this paper is simple, fast and practical. Next, let the editor take you to learn "what is the content of the linux makefile file"?

# sample Makefile

Edit: main.o kbd.o command.o display.o\ # * times: appears as a list of dependent files for the target "edit"

Insert.o search.o files.o utils.o

Cc-o edit main.o kbd.o command.o display.o\ # second time: list of parameters on the rule command line as "cc"

Insert.o search.o files.o utils.o

Main.o: main.c defs.h

Cc-c main.c

Kbd.o: kbd.c defs.h command.h

Cc-c kbd.c

Command.o: command.c defs.h command.h

Cc-c command.c

Display.o: display.c defs.h buffer.h

Cc-c display.c

Insert.o: insert.c defs.h buffer.h

Cc-c insert.c

Search.o: search.c defs.h buffer.h

Cc-c search.c

Files.o: files.c defs.h buffer.h command.h

Cc-c files.c

Utils.o: utils.c defs.h

Cc-c utils.c

Clean:

Rm edit main.o kbd.o command.o display.o\

Insert.o search.o files.o utils.o

When writing, a longer line can be split into multiple lines using a backslash (\), which makes the Makefile clear and easy to read. Note: there can be no spaces after the backslash (this is also the most common mistake, and the mistake is more hidden). When writing Makefile, the recommender breaks down the longer lines into a way of using backslashes to connect multiple lines. When we finish the Maekfile; create the executable program "edit", all you have to do is type the command "make" in the directory that contains the Makefile (and, of course, the directory where the code is located). To delete the generated files and all .o files in this directory, just type the command "make clean".

In order to avoid the problem of repetitive work when writing code, the preferred approach in practice is to use a variable "objects", "OBJECTS", "objs", "OBJS", "obj" or "OBJ" as a substitute for the list of all .o files. Use this variable instead where these file lists are used. In the Makefile example above, you can add a line like this:

Objects = main.o kbd.o command.o display.o\

Insert.o search.o files.o utils.o

"objects", as a variable, represents a list of all .o files. After defining this variable, we can use "$(objects)" to represent it where we need to use the .o file list, rather than listing all the .o files. So the rule of the above example can be written as follows:

Objects = main.o kbd.o command.o display.o\

Insert.o search.o files.o utils.o

Edit: $(objects)

Cc-o edit $(objects)

…… .

…… .

Clean:

Rm edit $(objects)

When you need to add or remove an .o file. We just need to change the definition of "objects" (add or remove several .o files). This not only reduces the workload of maintenance, but also avoids the possibility of errors caused by omissions.

When you use make to compile a .c source file, you can omit the command used to compile a .c file. This is because make has a default rule that automatically compiles .c files and generates corresponding .o files. It executes the command "cc-c" to compile the .c source file. For the example above, the default rule uses the command "cc-c main.c-o main.o" to create the file "main.o".

When writing Makefile, if you use the implied rules of make for a .c file, it will automatically be regarded as a dependent file of the corresponding .o file (corresponding to: two files with the same file name except the suffix). So we can also omit the dependency .c file of the target in the rule.

The above example can be written in a simpler way, using the variable "objects". Simplified version of Makefile

The GUN make Chinese manual is as follows:

# sample Makefile

Objects = main.o kbd.o command.o display.o\

Insert.o search.o files.o utils.o

Edit: $(objects)

Cc-o edit $(objects)

Main.o: defs.h

Kbd.o: defs.h command.h

Command.o: defs.h command.h

Display.o: defs.h buffer.h

Insert.o: defs.h buffer.h

Search.o: defs.h buffer.h

Files.o: defs.h buffer.h command.h

Utils.o: defs.h

.PHONY: clean

Clean:

Rm edit $(objects)

The way to write rule recommendations is: single goal, multi-dependence. That is to say, try to make sure that there is only one target file in a rule, but there are multiple dependent files. Try to avoid a multi-objective, single-dependent approach. In this way, later maintenance will be very convenient, and the Makefile will be clearer and clearer.

.PHONY: clean

Clean:

-rm edit $(objects)

There are two differences between the two implementations:

Declare the "clean" goal as a pseudo-target through the ".PHONY" special target. Prevents the command of the rule of "clean" from not being executed when a file named "clean" exists on disk. two。 Using "-" before the command line means ignoring the execution error of the command "rm".

By default, make looks for linux makefile files in the working directory (the directory where make is executed) in the order of file names: "GNUmakefile", "makefile", "Makefile".

If the make program cannot find any of the above three files in the working directory, it will not read any other files as parsing objects. When the name of the linux makefile file is not any of these three, you need to specify the makefile file read by make through the "- f" or "--file" options of make. Give make the format of the makefile file: "- f NAME" or "- file=NAME", which specifies the file "NAME" as the linux makefile file to read when make is executed. You can also specify multiple makefile files to be read through multiple "- f" or "--file" options, and multiple makefile files will be concatenated in the specified order and parsed by make. When you specify make to read makefile's files through "- f" or "--file", make no longer automatically looks up the three standard-named makefile files.

At this point, I believe you have a deeper understanding of "what is the content of the linux makefile file?" you might as well do it in practice. Here is the website, more related content can enter the relevant channels to inquire, follow us, continue to learn!

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