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This article mainly introduces the use of MII and RMII interface in STM32 network. It is very detailed and has certain reference value. Friends who are interested must finish reading it.

The SMI interface is mainly used for communicating with external PHY chips and configuring PHY registers.

The data flow of real network communication is not transmitted through the SMI interface, but through the MII interface or RMII.

1. MII interface

The Media Independent Interface (MII) defines the interconnection between the MAC sublayer and the PHY at data rates of 10 Mbit/s and 100 Mbit/s.

Introduction to pin definition:

MII_TX_CLK: continuous clock signal. The signal provides a reference timing for TX data transmission. The nominal frequency is 2.5 MHz; when the rate is 10 Mbit/s and 25 MHz when the rate is 100 Mbit/s.

MII_TXD [3:0]: data sends signals. The signal is a group of four data signals, synchronously driven by the MAC sublayer, and is a valid signal (valid data) only when the MII_TX_EN signal is valid. MII_TXD [0] is the lowest significant bit and MII_TXD [3] is the highest significant bit. When MII_TX_EN is disabled, sending data does not have any impact on PHY.

MII_TX_EN: send an enable signal. This signal indicates that MAC is currently sending half bytes for MII. The signal must be synchronized with the first half of the header (MII_TX_CLK) and must be synchronized when all half bytes to be sent are sent to MII.

MII_RX_CLK: continuous clock signal. The signal provides a reference timing for RX data transmission. The nominal frequency is 2.5 MHz; when the rate is 10 Mbit/s and 25 MHz when the rate is 100 Mbit/s.

MII_RXD [3:0]: data receive signal. The signal is a group of four data signals, driven synchronously by PHY, and is a valid signal (valid data) only when the MII_RX_DV signal is valid. MII_RXD [0] is the lowest significant bit and MII_RXD [3] is the highest significant bit. When MII_RX_DV is disabled and MII_RX_ER is enabled, a specific MII_RXD [3:0] value is used to transmit specific information from PHY.

MII_RX_ER: receives an error signal. The signal must maintain one or more cycles (MII_RX_CLK) to indicate to the MAC sublayer that an error was detected somewhere in the frame. The error condition must be validated by MII_RX_DV.

MII_RX_DV: receive data valid signal. This signal indicates that PHY is currently receiving half bytes that have been recovered and decoded for MII. The signal must be synchronized (MII_RX_CLK) with the first half of the recovery frame and remain synchronized until the last half of the recovery frame. The signal must be disabled before the first clock cycle that follows the last half byte. In order to receive the frame correctly, the MII_RX_DV signal must cover the frame to be received in the time range, and its start time must not be later than the time when the SFD field appears.

MII_CRS: carrier sense signal. When the transmitting or receiving medium is not idle, the signal is enabled by the PHY. When both the transmitting and receiving media are idle, the signal is prohibited by the PHY. The PHY must ensure that the MII_CS signal remains valid under collision conditions. The signal does not need to be synchronized with the TX and RX clocks. In full-duplex mode, the signal makes no sense.

MII_COL: collision detection signal. After detecting a conflict on the media, PHY must immediately enable the conflict detection signal, and the conflict detection signal must remain in a valid state as long as there is a conflict condition. The signal does not need to be synchronized with the TX and RX clocks. In full-duplex mode, the signal makes no sense.

MDC:MDC signal belongs to SMI interface. For more information, please see "SMI Interface of STM32 Network".

MDIO:MDIO signal belongs to SMI interface. For more information, please see "SMI Interface of STM32 Network".

The following figure shows TX interface signal coding

The following figure shows RX interface signal coding

Clock source of MII interface

To generate TX_CLK and RX_CLK clock signals, the 25MHz clock must be provided to the external PHY, as shown in the figure. In addition to using an external 25 MHz quartz crystal to provide the clock, the signal can also be output through the MCO pin of the STM32F20xx microcontroller. In this case, the PLL frequency doubling must be configured to obtain the desired frequency on the MCO pin through a 25 MHz external quartz crystal.

Corresponding code

/ * Enable GPIOs clocks * / RCC_AHB1PeriphClockCmd (RCC_AHB1Periph_GPIOA,ENABLE); / * Enable SYSCFG clock * / RCC_APB2PeriphClockCmd (RCC_APB2Periph_SYSCFG, ENABLE); / * Configure MCO (PA8) * / GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL GPIO_Init (GPIOA, & GPIO_InitStructure); / * Output HSE clock (25MHz) on MCO pin (PA8) to clock the PHY * / RCC_MCO1Config (RCC_MCO1Source_HSE, RCC_MCO1Div_1); 2. RMII interface

Reduced media-independent interface: RMII (Compact Media Independent Interface). The Compact Media Independent Interface (RMII) specification reduces the number of pins between the microcontroller Ethernet peripherals and the external PHY at 10pm and 100Mbit/s.

According to the IEEE 802.3u standard, MII includes 16 pins for data and control signals. The RMII specification reduces the number of pins to 7 (the number of pins reduced by 62.5%). The meaning of the pin can be referred to the MII interface.

The RMII interface is an instantiated object between MAC and PHY. These help convert the MII interface of MAC to the RMII interface. The RMII interface has the following characteristics

The running rate of 10-Mbit/s and 100-Mbit/s

The reference clock must be 50 MHz

The same reference clock must be provided externally to MAC and external Ethernet PHY

It provides independent 2-bit wide (two-bit) send and receive data paths.

There are fewer clock pins than MII interface here, and there is a very important point, that is, the clock source of RMII interface must be 50MHZ.

RMII interface clock source

The STM32F207xx controller can provide the 50MHz clock signal from the MCO pin, of course, the user needs to configure PLL to generate this clock.

Use external 50 MHz clock to drive PHY or use embedded PLL to generate 50 MHz frequency signal to drive PHY.

3. The corresponding pins of the two interfaces

STM32F207VCT6 (100pin) chip

Ethernet pins configurationETH_MDIO-> PA2 pin 25ETH_MDC-- > PC1 pin 16ETH_PPS_OUT-- > PB5 pin 91ETH_MII_CRS- -- > PA0 pin 23ETH_MII_COL-- > PA3 pin 26ETH_MII_RX_ER-> PB10 pin 47ETH_MII_RXD2-> PB0 pin 35ETH_MII_RXD3- > PB1 pin 36ETH_MII_TX_CLK-> PC3 pin 18ETH_MII_TXD2-> PC2 pin 17ETH_MII_TXD3-> PB8 pin 95 ETHMIIR PC2 pin 17ETH_MII_TXD3 CLK > ETHMIIREFLIKUR-> PA1 pin 24ETH_MII_RX_DV/ETH _ RMII_CRS_DV-> PA7 pin 32ETH_MII_RXD0/ETH_RMII_RXD0-> PC4 pin 33ETH_MII_RXD1/ETH_RMII_RXD1-> PC5 pin 34ETH_MII_TX_EN/ETH_RMII_TX_EN-> PB11 pin 48ETH_MII_TXD0/ETH_RMII_TXD0-> PB12 pin 51ETH_MII_TXD1/ETH_RMII_TXD1-> PB13 pin 52

The ETH_PPS_OUT pin ST is officially shielded by demo and does not belong to either the MII API or the RMII interface. We will not enter the statistics below.

MII has 15 interfaces plus SMI interface, a total of 17 pins. (there are no pins for the 25MHz clock)

RMII has 7 interfaces plus SMI interface, a total of 9 pins.

In addition to the pin corresponding to the MII API and RMII API that I have calculated by myself, the ST official also gives the corresponding figure in the reference manual, as follows:

4. The choice of MII and RMII

Use the 23 configuration bit MII_RMII_SEL in the SYSCFG_PMC register (note: unlike F107, which is the AFIO_MAPR register), choose MII or RMII mode. Before the Ethernet controller is in reset mode or enable clock, the application must set MII/RMII mode.

The corresponding ST library function is

/ / function input parameters can be selected as follows / / SYSCFG_ETH_MediaInterface_MII: MII mode selected//SYSCFG_ETH_MediaInterface_RMII: RMII mode selectedvoid SYSCFG_ETH_MediaInterfaceConfig (uint32_t SYSCFG_ETH_MediaInterface)

MII/RMII internal clock scheme

Support MII and RMII as well as clock schemes required for 10 and 100 Mbit/s operations, as shown in the following figure.

Note in the red box above: HCLK must be greater than 25MHz. This problem point has been mentioned in the previous article "SMI Interface of STM32 Network". Again, it is mentioned here that if this condition is not met, there may be strange problems and difficult to find.

In the official manual, there is another sentence.

To save pins, the RMII_REF_CK and MII_RX_CLK input clock signals need to be multiplexed on the same GPIO pin.

These are all the contents of the article "what is the use of MII and RMII interfaces in STM32 networks". Thank you for reading! Hope to share the content to help you, more related knowledge, welcome to follow the industry information channel!

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