Shulou(Shulou.com)06/01 Report--

This article shows you how to understand the tool language commonly used for GNU gcc compilation, makefile, which is concise and easy to understand, which can definitely brighten your eyes. I hope you can get something through the detailed introduction of this article.

LiteOS source code using makefile for file batch compilation and link to the generated file, if using LiteOS to design the project using the GNU compiler for compilation, generally will be used to compile and link the program to makefile, if the use of Keil or IAR compiler for compilation, then in Keil IDE or IAR IDE to set the compiler information and file package path can be compiled links and output files.

1. Makefile introduction

To put it simply, makefile is a file executed by make. The process of turning code into a feasibility file is called compilation, and the compilation of a series of files is called build. Make is a construction tool provided by GNU, which mainly uses the build and compilation process of C, C++ projects. To learn to use Make, we need to learn to write in makefile, makefile. This file describes how to compile and link a text editor consisting of several C source files and several header files. When explicitly required, makefile can also tell make how to run other commands (for example, delete some files as a cleanup operation)

1.1 makefile rules

A simple makefile consists of "rules" with the following shapes:

Target... : prerequisites... Recipe... ...

The target (target) is usually the name of the file generated by the program. An example of a target is an executable file or an object file. The target can also be the name of the operation to be performed, such as "clean"

The prerequisites (precondition) is a file that is used as input to the creation target. A goal usually depends on several files.

Recipe (command) is an action to be performed. Recipes may have multiple commands on the same line or on their own lines. Please note: you need to add a tab at the beginning of each recipe line! This is a vague place that has attracted people's attention. If you want to use characters other than tabs as prefixes in your recipe, you can set the .RECIPEPREFIX variable to other characters

Goals are required and cannot be omitted; prerequisites and commands are optional, but there must be at least one of them.

A rule describes how and when to reproduce certain files that are the target of a particular rule. Make executes the method based on the prerequisites for creating or updating the target. Rules can also explain how and when to perform an action. A makefile may contain text other than rules, but a simple makefile only needs to contain rules. The rules may seem a little more complex than shown in this example, but all the rules are more or less appropriate for the pattern.

1.2Makefile syntax

① # for comments

② wildcards are used to specify a set of file names that match the criteria. The wildcard characters of Makefile are the same as those of Bash, mainly including asterisk (*) and question mark (? ) and [.]. For example, *. O represents all files with the suffix o.

③% pattern matching

If you need to compile the a.c and b.c files in the current directory, the original way to write them is:

A.o: a.cb.c: b.c

Using% can be abbreviated as:

%. O:%. C

% abbreviated files can be used when dealing with a large number of files of the same type.

④ "=" custom variable

Txt = Hello Worldtest: @ echo $(txt)

The above txt replaces "Hello World".

At the same time, based on "=" Makefile, it provides (=,: =,? =, + =) four assignment operations.

⑤ built-in variables

Make has its own operation variables, especially some of its own functional commands; for example, $(CC) points to the compiler currently in use, and $(MAKE) points to the currently used Make tool.

For more information on specific variable rules, please see https://www.gnu.org/software/make/manual/html_node/Implicit-Variables.html.

⑥ automatic variable (Automatic Variables)

Makefile provides some rule-related variables, commonly used as follows:

(1) $@-refers to the current target

(2) $<-refers to the first precondition

A.txt: b.txt c.txt cp $< $@

The above code is consistent with the following code

A.txt: b.txt c.txt cp b.txt a.txt

$< refers to the first precondition, that is, "b.txt"; $@ refers to the target value, namely "a.txt"

(3) $?-refers to all prerequisites that are newer than the target, separated by spaces. For example, the rule is t: p1p2, where the timestamp of p2 is newer than t, $? It refers to p2.

(4) $^-refers to all preconditions, separated by spaces. For example, if the rule is t: p1p2, then $^ refers to p1p2.

(5) $*-refers to the part of the% match, such as% match F1 in f1.txt, and $* represents F1.

(6) $(@ D) and $(@ F)-point to the directory name and file name of $@, respectively. For example, if $@ is src/input.c, then the value of $(@ D) is src and the value of $(@ F) is input.c.

(7) $(

Welcome to subscribe "Shulou Technology Information " to get latest news, interesting things and hot topics in the IT industry, and controls the hottest and latest Internet news, technology news and IT industry trends.