Shulou(Shulou.com)06/03 Report--

This article mainly introduces "how to solve the problem of SysTick timer error". In daily operation, I believe many people have doubts about how to solve the problem of SysTick timer error. The editor consulted all kinds of data and sorted out simple and easy-to-use operation methods. I hope it will be helpful to answer the doubt of "how to solve the problem of SysTick timer error". Next, please follow the editor to study!

The origin of the 01 pit

The systick timer is used. The specific code is as follows

Void delay_us (uint32_t nus) {uint32_t temp; SysTick- > LOAD = RCC_Clocks.HCLK_Frequency/1000000/8*nus; SysTick- > VAL=0X00;// emptying counter SysTick- > CTRL=0X01;// enable, reduce to zero is no action, use external clock source do {temp=SysTick- > CTRL;// to read the current countdown} while ((temp&0x01) & (temp& (1VAL = 0X00) / / emptying counter} void delay_ms (uint16_t nms) {uint32_t temp; SysTick- > LOAD = RCC_Clocks.HCLK_Frequency/1000/8*nms; SysTick- > VAL=0X00;// emptying counter SysTick- > CTRL=0X01;// enable, reducing to zero means no action. External clock source do {temp=SysTick- > CTRL;// is used to read the current countdown value} while ((temp&0x01) & (temp& (1VAL = 0X00) / / clear the counter}

For "four methods of STM32 delay", what is said in the article is as follows

This is the reason for / 8 in the following code.

SysTick- > LOAD = RCC_Clocks.HCLK_Frequency/1000/8*nms

I believed it and found "evidence" in the STM32F207 reference manual (RM0033).

In the picture above, there is a direct 8-division at ①, unlike the one from ②, 1, 2, 4, and 8. So I'm sure it's the SYSTICK clock that is fixed to the HCLK clock.

When I was learning RTThread, I saw the following code to configure the SysTick customizer

There are a lot of question marks in my heart, the official manual of STM32, which clearly says that the clock of SYSTICK is fixed as the 1x8 of HCLK clock. I use an oscilloscope to measure that there is no problem with the configuration of RTThread and the time delay can be normal.

02 fill the pit

Bit 2 sets 1, which indicates that the clock rate is AHB, which is the default 120000000Hz.

Bit 2 clears 0, indicating that the clock rate is AHB/8, that is, 120000000/8Hz.

RTThread is configured as an internal clock

The previous article was configured as an external clock source

I didn't pay attention to this detail, which made me a little confused when I looked at the RTThread code.

The exact description is:

The clock of the SYSTICK can be 1 or 8 of the HCLK clock. Here we choose an external clock source of 120m, so the clock of the SYSTICK is (120beat 8) M.

It is hereby corrected.

At this point, the SysTick_Config function provided by STM32's standard peripheral library also uses an internal clock.

/ * *\ brief System Tick Configuration This function initialises the system tick timer and its interrupt and start the system tick timer. Counter is in free running mode to generate periodical interrupts. \ param [in] ticks Number of ticks between two interrupts\ return 0 Function succeeded\ return 1 Function failed * / static _ INLINE uint32_t SysTick_Config (uint32_t ticks) {if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); / * Reload value impossible * / SysTick- > LOAD = (ticks & SysTick_LOAD_RELOAD_Msk)-1 / * set reload register * / NVIC_SetPriority (SysTick_IRQn, (1CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; / * Enable SysTick IRQ and SysTick Timer * / return (0); / * Function successful * /}

Call method, generate 1ms interrupt call method

SysTick_Config (SystemCoreClock / 1000)

With regard to the selection of clock sources, in addition to operating registers, there are library functions that can be selected.

/ * * @ brief Configures the SysTick clock source. * @ param SysTick_CLKSource: specifies the SysTick clock source. * This parameter can be one of the following values: * @ arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. * @ arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. * @ retval None * / void SysTick_CLKSourceConfig (uint32_t SysTick_CLKSource) {/ * Check the parameters * / assert_param (IS_SYSTICK_CLK_SOURCE (SysTick_CLKSource)); if (SysTick_CLKSource = = SysTick_CLKSource_HCLK) {SysTick- > CTRL | = SysTick_CLKSource_HCLK;} else {SysTick- > CTRL & = SysTick_CLKSource_HCLK_Div8;}}

In addition to the above, I have found other evidence that the clock of the SYSTICK can be 1 or 8 of the HCLK clock.

In the STM32CubeMx configuration software, you can choose 1 division or 8 division.

03 modify code verification

Modify the code involved to 1 frequency division.

Void delay_ms (uint16_t nms) {uint32_t temp; SysTick- > LOAD = RCC_Clocks.HCLK_Frequency/1000*nms-1; SysTick- > VAL=0X00;// emptying counter SysTick- > CTRL=0X01; SysTick_CLKSourceConfig (SysTick_CLKSource_HCLK); do {temp=SysTick- > CTRL;// reads the current countdown value} while ((temp&0x01) & & (temp& (1VAL = 0X00WTA / emptying counter)

And then call

GPIO_SetBits (GPIOE,GPIO_Pin_4); / / turn off LED light delay_ms (500); / / delay 500ms GPIO_ResetBits (GPIOE,GPIO_Pin_4); / / turn on LED light delay_ms (500); / / delay 500ms

If you step into another pit, the delay is not correct.

The reason is: at this time, the SYSTICK clock frequency is the 24-bit countdown timer of 120MHz, that is, a cycle, at most timing 139.810125ms. Cannot delay 500ms.

Correct a previous error here, as shown in the following figure

We subtract 1 from the value of this counter, which is more accurate.

At this point, the study on "how to solve the problem of SysTick timer error" is over. I hope to be able to solve your doubts. The collocation of theory and practice can better help you learn, go and try it! If you want to continue to learn more related knowledge, please continue to follow the website, the editor will continue to work hard to bring you more practical articles!

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