Shulou(Shulou.com)06/01 Report--

In this issue, the editor will bring you about the abnormal solution of Keil MDK floating point support. The article is rich in content and analyzes and describes it from a professional point of view. I hope you can get something after reading this article.

When you call printf to debug a floating-point number, it is represented correctly in memory, but the print data is 0.00, and the other shaping data is normal.

According to the data, floating-point number requires stack octet alignment, and this problem will occur if the default stack of the system is not octet alignment.

Just align the variable octets.

Solution:

1. Solution under IAR:

Specify the number of aligned bytes through # pragma data_alignment

For example:

# pragma data_alignment=8 OS_STK Task1_LED1_ Stk [Task 1 _ LED1_Stk_Size]; # pragma data_alignment=8 OS_STK Task2_backlight_ Stk [Task 2 _ backlight_Stk_Size]

2. Solution under Keil MDK:

Add a mandatory octet alignment command before the task stack declaration, as follows:

_ _ align (8) static OS_STK TaskEquipmentStk [task _ EQUIPMENT_STK_SIZE]; _ _ align (8) static OS_STK TaskUartRcvStk [task _ UARTRCV_STK_SIZE]; _ _ align (8) static OS_STK TaskFileRcvStk [task _ FILERCV_STK_SIZE]; _ _ align (8) static OS_STK TaskFtpStk [TASK_FTP_STK_SIZE]; _ align (8) static OS_STK TaskErrorRateRS485Stk [TASK_ERROR_RATE_RS485_STK_SIZE]

The history of this is that ARM itself does not support unaligned data access; therefore, with 64Bit's data manipulation instructions, the instructions require 8-byte alignment.

Furthermore, after a certain version of the compiler (RVCT3? AAPCS requires 8-byte alignment of the stack

There is an 8-byte aligned AAPCS before there is a CM3. Pay attention to the order. Before CM3 r2p0, automatic stack does not require 8 alignment, r2p0 seems to be mandatory alignment.

Printf's 8 alignment is required by the C runtime and has nothing to do with hardware. C RTL manuals are written and can be read. It is rooted in AAPCS requirements, while AAPCS is rooted in instructions such as LDRD.

In other words, if 128Bit data operations are available in the future and ARM does not support misalignment, then AAPCS may be upgraded to 16-byte alignment.

This is what the abnormal solution of Keil MDK floating-point support shared by Xiaobian is. If you happen to have similar doubts, please refer to the above analysis to understand. If you want to know more about it, you are welcome to follow the industry information channel.

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