Shulou(Shulou.com)06/02 Report--

1. Overview

This design uses FPGA technology, the video data of CMOS camera (LVDS interface) is collected, stored, frame rate conversion and format conversion, and finally displayed on the computer screen through the USB2.0 interface.

two。 Hardware system block diagram

CMOS uses a global exposure chip, FPGA uses ALTERA's CYCLONE IV,FLASH, EPCS64,DDR2 uses Hynix's 1Gb memory, and USB2.0 uses Cypress's 68013 chip.

3. FPGA logic block diagram

Each part of the logic module of FPGA is shown in the following figure:

LVDS Decode, decode CMOS camera video data

I2C Master, configure CMOS chip

DDR2 Control, configure and control DDR2 chipset to achieve read-write arbitration

FIFO Write, which writes the captured video data into DDR2 across the clock domain.

FIFO Read, which reads the data in DDR2 across the clock domain to the subsequent image processing module

Frame Buffer, responsible for scheduling FIFO Write and FIFO Read, realizing frame rate conversion

USB Control, accepts the request of USB PHY, requests data from DDR2 through FIFO Read, and customizes the package and sends it to USB PHY chip.

4. Global exposure

Global exposure is an improvement for line-by-line exposure. Under line-by-line exposure, sensor is exposed line by line according to the behavior unit, so that when there is a high-speed relative motion between the subject and the sensor, the image will be distorted in shape and color, as shown in the following figure:

On the other hand, the global exposure is carried out in frames, which can capture objects moving at high speed without deformation.

5. LVDS decoding

The camera chip provides differential serial interface (LVDS), which supports 1-2-4 Data lane to transmit image 8-10-12 bit data. In this paper, the transmission timing of four data lane modes embedded in synchronization signals are introduced.

6. CMOS configuration

CMOS sensor supports video output of up to 1.3 million pixels and 240 frames.

SpiWriteRegister(0x01,0x03,0x01);// soft resetSpiWriteRegister(0x01,0x00,0x00);SpiWriteRegister(0x30,0x34,0x01);SpiWriteRegister(0x30,0x35,0xc2);SpiWriteRegister(0x33,0x0b,0x4c);SpiWriteRegister(0x36,0x64,0x09);SpiWriteRegister(0x36,0x38,0x82);SpiWriteRegister(0x3d,0x08,0x00);SpiWriteRegister(0x36,0x40,0x03);SpiWriteRegister(0x36,0x28,0x07);SpiWriteRegister(0x32,0x05,0x93); //rncSpiWriteRegister(0x36,0x20,0x42);SpiWriteRegister(0x36,0x23,0x06);SpiWriteRegister(0x36,0x27,0x02);SpiWriteRegister(0x36,0x21,0x28);SpiWriteRegister(0x36,0x3b,0x00);SpiWriteRegister(0x36,0x33,0x24);SpiWriteRegister(0x36,0x34,0xff); //fpn optimizeSpiWriteRegister(0x34,0x16,0x10);SpiWriteRegister(0x3e,0x03,0x0b);SpiWriteRegister(0x3e,0x08,0x03);SpiWriteRegister(0x3e,0x09,0x20); SpiWriteRegister(0x3e,0x01,0x23);SpiWriteRegister(0x3e,0x14,0xb0);SpiWriteRegister(0x33,0x0b,0x40);SpiWriteRegister(0x3e,0x08,0x3f);SpiWriteRegister(0x36,0x3b,0x80);SpiWriteRegister(0x36,0x23,0x07);SpiWriteRegister(0x50,0x00,0x01);SpiWriteRegister(0x3e,0x01,0x00);SpiWriteRegister(0x3e,0x02,0x30);SpiWriteRegister(0x32,0x0c,0x05);SpiWriteRegister(0x32,0x0d,0x46);SpiWriteRegister(0x32,0x0e,0x02);SpiWriteRegister(0x32,0x0f,0x58);SpiWriteRegister(0x36,0x38,0x85);SpiWriteRegister(0x33,0x06,0x50);SpiWriteRegister(0x33,0x0b,0x68);SpiWriteRegister(0x33,0x08,0x10);SpiWriteRegister(0x3e,0x01,0x00);SpiWriteRegister(0x36,0x3b,0x00);SpiWriteRegister(0x36,0x63,0xf8); SpiWriteRegister(0x36,0x64,0x0a);SpiWriteRegister(0x36,0x33,0x27);SpiWriteRegister(0x30,0x3a,0x3a);SpiWriteRegister(0x30,0x3a,0x3a);SpiWriteRegister(0x30,0x3a,0x3a);SpiWriteRegister(0x30,0x3a,0x3a);SpiWriteRegister(0x36,0x3b,0x00);SpiWriteRegister(0x34,0x16,0x38);SpiWriteRegister(0x3e,0x08,0x23);SpiWriteRegister(0x3c,0x00,0x41); //FIFO RESET for mipiSpiWriteRegister(0x30,0x19,0x00);SpiWriteRegister(0x30,0x31,0x0a); // 10bitSpiWriteRegister(0x30,0x00,0x00);SpiWriteRegister(0x30,0x01,0x00);SpiWriteRegister(0x30,0x39,0x20);SpiWriteRegister(0x30,0x3a,0x31);SpiWriteRegister(0x30,0x3b,0x02);SpiWriteRegister(0x30,0x3c,0x08);SpiWriteRegister(0x4b,0x00,0xa2); //must SpiWriteRegister(0x30,0x22,0x19); //mustSpiWriteRegister(0x30,0x3f,0x01); //mustSpiWriteRegister(0x30,0x30,0x04); //mustSpiWriteRegister(0x30,0x2b,0xa0); //mustSpiWriteRegister(0x36,0x20,0x43);SpiWriteRegister(0x36,0x21,0x18);SpiWriteRegister(0x45,0x01,0xc0);SpiWriteRegister(0x45,0x02,0x16); //br recieve inv offSpiWriteRegister(0x36,0x23,0x07);SpiWriteRegister(0x50,0x00,0x01);SpiWriteRegister(0x36,0x20,0x43);SpiWriteRegister(0x33,0x00,0x30);SpiWriteRegister(0x3e,0x01,0x14);SpiWriteRegister(0x36,0x3b,0x80);SpiWriteRegister(0x36,0x64,0x0a);SpiWriteRegister(0x3e,0x08,0x23);SpiWriteRegister(0x34,0x16,0x00);SpiWriteRegister(0x36,0x33,0x20);SpiWriteRegister(0x36,0x33,0x23);SpiWriteRegister(0x32,0x11,0x0c); SpiWriteRegister (0x3ere0x0frec 0x05); SpiWriteRegister (0x36rex 0x3breo 0x08); / fpnSpiWriteRegister (0x3eEng 0x3reel 0x3je 0x22); / / nvddSpiWriteRegister (0x3rec 0x02rem 0x0c); / / rst go lowSpiWriteRegister (0x3e retro 0x83e 0x00a); / / pbias en rise edgeSpiWriteRegister (0x36prit 0x23m0x0x0x00x04); SpiWriteRegister (0x3pr 0x82e 0x0f); / sa fall edgeSpiWriteRegister (0x3ej0x0fjo 0x84); / gainSpiWriteRegister (0x3eprime 0x0b0x0x03); / gainSpiWriteRegister (0x3eprime 0x08nor0x0x27); SpiWriteRegister (0x3em0x08x23); SpiWriteRegister (03x6x0x06x005); / SpiWriteRegister (0x3x0b0b0x068); (0x0x068) SpiWriteRegister (0x068); SpiWriteRegister (0x5b repertory 0x02recorder 0x01); SpiWriteRegister (0x5b repertory 0x03repert0x01); SpiWriteRegister (0x36retro 0x3b 0x02); SpiWriteRegister (0x36rewards 0x32mem0x54); SpiWriteRegister (0x36mem0x3recover0x32); SpiWriteRegister (0x34hel0x16mei 0x0e); SpiWriteRegister (0x36recover0x0x0e); SpiWriteRegister (0x36recover0x6j0x88); SpiWriteRegister (0x36Zhejiang 0x0bj0x50); SpiWriteRegister (0x3recital 0x22writ 0x06); / blksunSpiWriteRegister (0x3prime 0x0xfore30xb3); SpiWriteRegister (0x34mor 16x011); SpiWriteRegister (0x0x00x001)

7. USB2.0 PHY

Cypress's EZ-USB FX2 is the world's first integrated USB2.0 microprocessor, which integrates USB2.0 transceiver, SIE (serial interface engine), enhanced 8051 microcontroller and programmable peripheral interface.

8. USB Slave FIFO transmission

When a master connected to the chip only needs to use FX2 as a USB2.0 interface to realize high-speed communication with the host, and it can provide the transmission timing that meets the requirements of Slave FIFO, the Slave FIFO transmission mode can be adopted.

In this way, the embedded 8051 firmware is only responsible for configuring Slave FIFO-related registers and controlling when FX2 works in Slave FIFO mode.

In Slave FIFO mode, the connection between the master logic and FX2 is shown in the following figure:

IFCLK: the output clock of FX2, which can be used as a synchronous clock for communication

FLAGA/FLAGB/FLAGC/FLAGD: FIFO status information output by FX2, such as full, empty, etc.

SLCS:FIFO chip selection signal, external logic control, when the SLCS output is high, data transmission cannot be carried out.

SLOE:FIFO output enable, external logic control, when SLOE is invalid, the data line does not output valid data

SLRD:FIFO read signal, external logic control, when reading synchronously, the rising edge of each IFCLK when the FIFO pointer is valid in SLRD is incremented, and in asynchronous reading, the FIFO read pointer is incremented along each valid-invalid jump of the SLRD.

SLWR:FIFO write signal, external logic control, synchronous write, rising time data of each IFCLK when SLWR is valid, FIFO pointer increment, asynchronous write, data is written along each valid-invalid jump of SLWR, FIFO write pointer is incremented

PKTEND: packet end signal, external logic control, under normal circumstances, the external logic writes to the FIFO of FX2. When the number of bytes written to the FIFO endpoint is equal to the packet size set by the FX2 firmware, the data will be automatically packed for transmission, but sometimes the external logic may need to transmit a packet with a number of bytes less than the packet size set by the FX2 firmware. In this case, it only needs to declare this signal after writing a certain number of bytes. At this time, no matter how many bytes are written by the external logic, the FX2 hardware automatically transmits it into a packet.

FD [15:0]: data line

FIFOADR [1:0]: select address lines for four FIFO endpoints, external logic control

Here, FIFO is set to asynchronous write mode, and the connected APIs are shown below:

The state machine of the standard asynchronous write mode is shown in the following figure:

IDLE: enter state 1 when a write event occurs

State 1: make FIFOADR [1:0] point to IN FIFO and enter state 2

Status 2: if the FIFO is full, enter waiting, otherwise enter status 3

State 3: get data, enable SLWR, invalid again, enter state 4

State 4: if you need to continue to transfer data, enter state 2, otherwise enter IDLE.

9. USB driver development

Microsoft's WDW DDK and VC++,DDK are available from http://www.microsoft.com/hwdev to develop EZ-USB drivers. Here we directly use a set of drivers provided by Cypress, which is sufficient to meet the general project requirements. Take the WIN7 64-bit driver as an example, the following three files are required:

Cyusb.sys 、 cyusbfx1_fx2lp.cat 、 cyusbfx1_fx2lp.inf .

What we need to modify is the cyusbfx1_fx2lp.inf file to add our PID/VID and descriptor (Shugen_VIP Device) to it.

; for x64 platforms [Device.NTamd64]% VID_2017&PID_0328.DeviceDesc%=CyUsb, USB\ VID_2017&PID_ 0328 [Strings] CYUSB_Provider = "Cypress" CYUSB_Company = "Cypress Semiconductor Corporation" CYUSB_Description = "Cypress Generic USB Driver" CYUSB_DisplayName = "Cypress USB Generic" CYUSB_Install = "Cypress CYUSB Driver Installation Disk" VID_2017&PID_0328.DeviceDesc= "Shugen_VIP Device" CYUSB.GUID= "{AE18AA60-7F6A-11d4-97DD-00010229B959}" CYUSB_Unused = "."

The drivers installed in device Manager are as follows:

10. Firmware program development

The firmware development of USB2.0 is completed under KEIL. Two target and library files of EZUSB USBJmp.OBJ and EZUSB.LIB are added to the project. There are three important source files under the project:

Fw.c, the abbreviation of FirmWare, and the communication of USB protocol are all completed here, including power-on enumeration, re-enumeration, wake-up and calling user programs and so on.

Periph.c, the user code is done here, and Cypress has set up a framework for us. The file includes void TD_Init (void), void TD_Poll (void), BOOL DR_VendorCmnd (void), void ISR_Ep0in (void) interrupt 0~void ISR_Ep8inout (void) interrupt 0 functions.

Dscr.51,USB descriptor file, including device descriptor, interface descriptor, endpoint descriptor, string, etc.

In order to synchronize the USB PHY chip and FPGA, we need to use the field synchronization signal vsync of the video to synchronize, and use the INT0 pin of 68013 to trigger the interrupt. The specific interrupt functions are as follows:

Void ISR_EXTR0 (void) interrupt 0 / / using 0 {if (frame_sign = = 1) {PA1 = 1; / / Enable p_w_picpath input} else {PA1 = 0; / / Disable p_w_picpath input / / Reset FIFO of EDP2 SYNCDELAY; FIFORESET = 0x80 / / activate NAK-ALL to avoid race conditions SYNCDELAY; FIFORESET = 0x02 reset / reset, FIFO 2 SYNCDELAY; FIFORESET = 0x00 Singapore / deactivate NAK-AL SYNCDELAY;}}

After designing the code, compile and generate HEX file (for online debugging, download to ram) and IIC file (for solidifying EEPROM).

11. Solidified code

To solidify the IIC file generated by KEIL compilation into EEPROM, you need to use the CyConsole tool provided by CYPRESS, as shown in the following figure:

If the curing is successful, you can see the specific information of the USB2.0 device in the CyConsole after reboot:

twelve。 Host computer DEMO software

Under Windows, VC++ can be used to develop application software. in the process of designing the host computer program of 68013, the API function and driver provided by CPYRESS are needed. The development package address is as follows:

Http://www.cypress.com/documentation/software-and-drivers/suiteusb-34-usb-development-tools-visual-studio

Supported operating systems:

Windows 2000 (w2K) Windows XP (wxp) Windows Vista (wlh) Windows 7

Supported CPU types:

X86 (32bit-i386) x64 (64bit-amd64)

The development process requires the use of both cyapi.h and cyapi.lib files. The CyAPI control function class mainly includes 8 control classes:

Transmission endpoint control class CCyBulkEndPoint, control transmission endpoint class CCyControlEndPoint, medium transmission terminal point control class CCyInterruptEndPoint, synchronous transmission terminal point control class CCyIsocEndPoint, device control class CCyUSBDevice, configuration information class CCyUSBConfig, endpoint control class CCyUSBEndPoint and interface control class CCyUSBInterface. For specific usage, please refer to Cypress CyAPI Programmer's Reference.

13. The final result

The following picture shows the picture of the fan taken with the mobile phone, and the shape of the fan blade can no longer be seen at all.

The picture below is a picture taken by the designed board, from which you can see the shape of the blade, even though the fan is spinning at high speed.

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