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2025-01-19 Update From: SLTechnology News&Howtos shulou NAV: SLTechnology News&Howtos > Internet Technology >
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Editor to share with you what is the use of the SMI interface in the STM32 network, I believe most people do not know much about it, so share this article for your reference, I hope you can learn a lot after reading this article, let's go to know it!
01. Introduction to Ethernet
Ethernet peripherals of STM32F20X and STM32F21 can accept and send data in accordance with the IEE802.3-2002 standard.
Ethernet provides a complete and flexible peripheral to meet different applications and requirements. It supports two standard industrial interfaces connected to the outside (PHY): the independent media interface (MII) and the compact media independent interface (RMII) defined in the IEEE802.3 specification are used by default. It can be used for a large number of requirements, such as switches (switches), network interface cards and so on.
Ethernet meets the following criteria:
● IEEE 802.3-2002 for Ethernet MAC.
The ● IEEE 1588-2008 standard, which is used to specify the accuracy of clock synchronization in the network.
● AMBA 2.0 for AHB master / slave ports.
The RMII specification of the ● RMII Alliance.
02. ETH introduction of STM32F207
STM32F207 supports the MII interface and the RMII interface. STM32F207 Ethernet peripherals include a MAC802.3 (Media access Control) and a DMA controller. It supports MII and RMII interfaces by default, switching through a select bit (refer to the SYSCFG_PMC register).
The DMA controller is connected to the memory through the AHB master-slave interface and the kernel. The AHB master interface controls data transmission, and the AHB slave interface is used for access control and status register (CSR) space.
Before the MAC kernel sends the data, the data is sent to the FIFO cache through DMA. Similarly, the receiving FIFO stores Ethernet data frames received over the line until they are transmitted to system memory via the DMA.
Ethernet peripherals also include a SMI for communicating with external PHY. Through the configuration of a set of registers, users can choose different modes and functions of MAC and DMA controllers.
When using Ethernet, the AHB clock must be at least 25MHZ.
The following is the block diagram of ETH
Connection information about AHB:
Area 1: we call it the SMI interface, which is used to configure external PHY chips.
Area 2: is the data exchange interface, that is, the MII interface and RMII interface we mentioned above.
03. SMI interface 3.1and station management interface: SMI
The station management interface allows any PHY register request to pass through the 2-wire clock and data line. This interface supports up to 32 PHY.
The application can select one of the 32 PHY and then select one of the 32 registers contained in any PHY to send control data or receive status information. Only one register in a PHY can be addressed at any given time.
Both MDC clock lines and MDIO data lines are used as multiplexing functions in microcontrollers.
MDC: periodic clock that provides a reference timing for data transmission at a maximum frequency of 2.5 MHz. The minimum high-level time and minimum low-level time of the MDC must both be 160 ns. The minimum cycle of MDC must be 400 ns. When idle, the SMI management interface drives the MDC clock signal to a low level.
MDIO: data input / output bitstream for synchronous transmission of status information to / from PHY devices via MDC clock signals.
3.2.The SMI frame structure
The following figure shows the frame structure of read and write operations, and bit transmission must be required from left to right.
Preamble (32bit leader): each transmission (read or write) must begin with the leading character, which is 32 consecutive logical'1' signals on the MDI line and 32 clock signals on the corresponding MDC line. This part of the signal is used to establish synchronization with PHY devices.
Start (start character): the start of a frame is defined as' 01', that is, the MDI line drops from logical'1' to'0' and back to'1' to mark the transmission.
Start.
Operation: used to define the type of operation: read or write.
The address of PADDR:PHY has 5 bits and can distinguish 32 PHY. High bits are sent and received first.
RADDR: registers have 5-bit addresses and can address 32 separate registers. High bits are sent and received first.
The steering character of the TA:2 bit, inserted between the RADDR and the DATA, to avoid conflicts during read operations. During the read operation, during the 2-bit time of the TA, the MAC controller maintains the high resistance state of the MDI line, while the PHY device first maintains the 1-bit high resistance state and outputs the'0' signal at the second bit. During the write operation, during the 2-bit time of the TA, the MAC controller drives the MDI line to output a '10' signal, while the PHY setting maintains a high resistance state.
DATA (data): 16-bit data field. Bit 15 of the ETH_MIID register is the first to send and receive.
Free bit: the MDIO line is kept in a state of high resistance. Cancel all three-state drivers, and the PHY pull-up resistor ensures that the MDIO line is logical'1'.
3.3.The SMI write operation
When the application sets the MII write and busy bits (Ethernet MACMII address register (ETH_MACMIIAR)), the SMI interface sends the PHY address and PHY register address to PHY, and then transfers data (Ethernet MACMII data register (ETH_MACMIIDR)). In the process of data transmission by SMI interface, the contents of MII address register and MII data register cannot be modified; in this process (busy bit is high), the write operation of MII address register or MII data register will be ignored and will not affect the correct completion of the whole transmission. When the write operation is completed, the SMI interface clears the busy bit and informs the application.
The following figure describes the frame format for write operations.
3.4.The SMI read operation
When the program sets the MII busy position of the Ethernet MACMII address register (ETH_MACMIIAR) to '1th, and keeps the MII write bit at' 0cm MII interface, it sends the PHY address and the PHY register address, and reads the PHY register. During the entire transmission process, the application cannot modify the contents of the MII address register and the MII data register. In the process of transmission (the busy bit is high), the write operation to the MII address register or MII data register will be ignored and will not affect the correct completion of the whole transmission. After the read operation is completed, the SMI interface clears the busy bit and updates the data read back from PHY to the MII data register.
The following figure describes the frame format of the read operation
3.5. SMI clock selection
MAC starts managing write / read operations. The SMI clock is a frequency division clock, and its clock source is the application clock (AHB clock). The frequency division factor depends on the clock range set in the MII address register. Now that we're talking about clocks, let's mention again what I mentioned above: when using Ethernet, the AHB clock must be at least 25MHZ.
04, Code
The initialization of the SMI interface of the network port of STM32 is very simple.
Initialize GPIO.
RCC_AHB1PeriphClockCmd (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOF, ENABLE); / * Enable SYSCFG clock * / RCC_APB2PeriphClockCmd (RCC_APB2Periph_SYSCFG, ENABLE); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;GPIO_Init (GPIOA, & GPIO_InitStructure); GPIO_PinAFConfig (GPIOA, GPIO_PinSource2, GPIO_AF_ETH); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;GPIO_Init (GPIOC, & GPIO_InitStructure) GPIO_PinAFConfig (GPIOC, GPIO_PinSource1, GPIO_AF_ETH)
Because the SMI interface requires MAC coordination, it needs to be a clock that enables MAC.
RCC_AHB1PeriphClockCmd (RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx | RCC_AHB1Periph_ETH_MAC_Rx, ENABLE)
The read and write functions of the SMI interface.
Uint16_t ETH_ReadPHYRegister (uint16_t PHYAddress, uint16_t PHYReg) uint32_t ETH_WritePHYRegister (uint16_t PHYAddress, uint16_t PHYReg,uint16_t PHYValue) these are all the contents of this article entitled "what is the use of SMI interfaces in STM32 networks?" Thank you for reading! I believe we all have a certain understanding, hope to share the content to help you, if you want to learn more knowledge, welcome to follow the industry information channel!
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