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Editor to share with you what is the use of ARM assembly instructions MRS and MSR. I hope you will get something after reading this article. Let's discuss it together.

There are two instructions in ARM to transfer data between the status register and the general register.

For 32-bit ARM processors, the status register is a 32-bit long register. The meaning of each bit is as follows:

It is divided into four parts:

1, conditional marker bit

N (Negative), Z (Zero), C (Carry) and V (Verflow) are collectively referred to as conditional marker bits. ARM instructions can be executed selectively according to these conditional flag bits in CPSR.

2Q mark bit

In the E-series processors of ARM v5, the bit [27] of CPSR is called the Q flag bit. It is mainly used to indicate whether the enhanced DSP instruction has overflowed.

3, control bit

I, F, T and M [4:0] are collectively referred to as the control bit. These bits change when an exception interrupt occurs. In privileged processor mode, the software can modify these control bits.

The following indicates the meaning of the control bit M [4:0]:

M [4:0]

Processor mode

Accessible register

0b10000

User mode

PC,CPSR, R14~R0

0b10001

FIQ mode

PC,CPSR, SPSR_fiq,R14_fiq,R8_fiq, R7~R0

0b10010

IRQ mode

PC,CPSR, SPSR_irq,R14_irq,R13_irq,R12~R0

0b10011

Management mode

PC,CPSR, SPSR_svc,R14_svc,R13_svc,R12~R0

0b10111

Abort mode

PC,CPSR, SPSR_abt,R14_abt,R13_abt, R12~R0

0b11011

No pattern defined

PC,CPSR, SPSR_und,R14_und,R13_und, R12~R0

0b11111

System mode

PC,CPSR (ARMv4 and above), R14~R0

4, reserved bit

For extensions to future versions of ARM.

The status register access instruction is only two days old:

MRS: a transfer instruction from a status register to a general register.

MSR: general register to status register transfer instructions.

Introduction of MRS instruction

Instruction encoding format of MRS:

The syntax format of the instruction:

MRS {}, CPSR

MRS {}, SPSR

Where:

The condition code for the execution of the instruction. The instruction is executed unconditionally when ignored.

Is the target register.

Pseudo code for instruction operation:

C code

If ConditionPassed (cond) then if R = = 1 then Rd = SPSR else Rd = CPSR

Where the MSR instruction is used:

The contents of the status register are usually modified through the read-modify-write-back operation sequence. The MRS instruction is used to read the contents of the status register into the general register.

When the exception allows nesting, you need to save the SPSR corresponding to the current processor mode after entering the exception interrupt and before the nested interrupt occurs. At this point, you need to read out the value of SPSR through the MRS instruction, and then save the SPSR value with other instructions.

You also need to save the value of the current state register when the process is switched.

Introduction of MSR instruction

Instruction encoding format of MRS:

There are two formats, one is that the original Operand is a general register, and the other is that the source Operand is an immediate number.

The syntax format of the instruction:

C code

MSR {} CPSR_, # MSR {} CPSR_, MSR {} CPSR_, # MSR {} CPSR_

Where:

The condition code for the execution of the instruction. The instruction is executed unconditionally when ignored.

Sets the bits that need to be operated in the status register. The 32 bits of the status register can be divided into four 8-bit fields:

F: indicates bits [31: 24], also known as conditional flag bit field

S: indicates bits [23: 16], also known as status flag bit field

X: indicates bits [15: 8], also known as extended bit field

C: indicates bits [7: 0], also known as control bit

For the immediate number to be transferred to the status register, the immediate number can be calculated to take care of

The register contains data to be transferred to the status register.

The pseudo code for the operation of the instruction:

The use of instructions:

The MSR instruction is usually used to restore or change the contents of the status register.

When exiting the exception interrupt processor program, if the contents of the state register are saved in advance, the contents of the state register are usually restored to the state register through the MSR instruction.

When the content of the status register needs to be modified, it is done through the "read-modify-write-back" instruction sequence. The writeback operation is also done through the MSR instruction.

The processor switches to privileged mode, using an example that will modify a bit field:

C code

Mrs R0, cpsr; read the values bic R0, R0, # 0x1F in cpsr; modify, remove the current processor mode orr R0, R0, # 0x13; modify, set privileged mode msr cpsr_c, R0; write back, only modify the control bits in CPRS

When the process switches to the application, SPSR_fsxc should be specified for full recovery.

After reading this article, I believe you have a certain understanding of "what is the use of ARM assembly instructions MRS and MSR". If you want to know more about it, you are welcome to follow the industry information channel. Thank you for reading!

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