Shulou(Shulou.com)06/01 Report--

In this issue, the editor will bring you about how to carry out IO pin constraints. The article is rich in content and analyzes and describes for you from a professional point of view. I hope you can get something after reading this article.

IO pin constraints are necessary for board verification of FPGA design, and they affect layout, routing and timing. There are three ways to perform pin constraints, one is through the VIvado pin constraint interface, one is through the command line, and the other is to import CSV files.

1. Visual interface mode

When the synthesis is completed, you can open the synthesis interface, and at this time you can see IO planning under layout, which is the IO constraint interface. The IO pins at the top of the design layer can be displayed in the interface, and we can also see the distribution map of the pins in the chip. The column direction is numbered in uppercase letters, starting from the top left corner A, and horizontally arranged with numbers, starting with 1. Areas of different colors represent different clock domains (IO bank). The pin functions provided by different IO bank are different, some IO bank may provide high-speed differential signals, some provide low-voltage pins, users can use flexibly according to their needs. To assign pins, you first need to distinguish which are ordinary pins and which are clock pins. From the interface, we can see that the hexagons are clock pins and the round ones are ordinary pins. Further magnification can also be seen that there is a Nline P pin that can be used for difference.

Next we can select pins in io ports. How we choose to save, we can save the pin constraint as a xdc file.

two。 Use xdc files to constrain

Set_property defines the pin properties, and get_ports gets the pin name. One here selects the pin name, and the other sets the voltage, both of which are often used.

3. Import the CSV file.

CSV is a standard file for FPGA pin constraints that appears to be displayed in tabular form and is very concise. Attributes such as IO bank,pin number,IO standard are defined. Users can fill in according to their needs.

Vivado also provides chip compatibility pin hints. For pins that encapsulate the same chips, the tool provides us with pin allocation functions that can be compatible with these chips at the same time. Select IO planning- > set part compatibility in tools, we can see the chips with the same package, and we can choose according to the needs of subsequent changes to the chip. After selection, the tool will tell us which pins are not common to all chips and which are compatible at the same time. Prohibit icons are displayed for those that cannot be shared.

The above is the editor for you to share how to carry out IO pin constraints, if you happen to have similar doubts, you might as well refer to the above analysis to understand. If you want to know more about it, you are welcome to follow the industry information channel.

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