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Today, I will talk to you about the example analysis of Clock Configration in STM32CubeMX. Many people may not know much about it. In order to make you understand better, the editor has summarized the following content for you. I hope you can get something according to this article.

In the project of creating STM32CubeMX, in addition to the selection of debugging mode, the focus is the configuration of the clock, that is, mainly for the configuration of RCC (Reset and Clock Control) in the program. Open Clock Configration in STM32F4's project and see the following interface:

What we do is very simple, because in the RCC option in Pinout&Configuration, we choose HSE as Crystal/Ceramic Resonator, so in Clock Configuration we configure the clock source as HSE, set it to 12MHZ (according to the actual hardware selection), select the coefficient of PLLM as 6-division, PLLN coefficient 200-fold, PLLP coefficient 4-division, and other parameters default, so we set the main frequency of the system (SYSCLK) to 100MHZ. As can be seen from the figure, as a basic project, our first task is to select the clock source of the system, determine the main frequency of the system, and then configure the clock of each bus according to the main frequency. Next, the parameters involved in this process are described.

1 hour clock source

STM32 has five clock sources, HSI, HSE, LSI,LSE and PLL, of which

The main results are as follows: (1) HSI is a high-speed internal clock, RC oscillator, frequency is 16MHz, the accuracy is not high. Can be directly used as a system clock or as a PLL clock input

(2) HSE is a high-speed external clock with quartz / ceramic resonator or clock source, and the frequency is 4MHz~26MHz.

(3) LSI is a low-speed internal clock, RC oscillator, frequency is 32kHz, provides low-power clock, mainly for independent watchdog and RTC

(4) LSE is a quartz crystal with low speed external clock and 32.768kHz frequency. Mainly used for RTC clock

(5) PLL is a phase-locked loop frequency doubling output. In PLL48CK, PLLP is used to generate high-speed system clock, PLLQ is used to generate USB OTG FS clock, random number generator clock and SDIO clock. The PLLR in PLLI2SCK is used to generate the I2S clock.

Among them, HSE,LSE and PLL can be used as system clock sources (SYSCLK).

2 bus and clock

After getting the system clock, the AHB (Advanced High-performance Bus) bus clock signal (HCLK) is obtained through a frequency divider, and the APB (Advanced Peripherals Bus) clock signal (PCLK) is obtained from the HCLK frequency division. HCLK is the clock signal provided for AHB bus, which is mainly used for

(1) memory controller, interrupt controller, LCD controller, DMA and other high-speed peripherals

(2) the system clock (Cortex System Timer) is obtained through the frequency divider, which is usually 8-frequency division. The system clock is used for tick-tock timer.

(3) CPU core supplies clock signal (FCLK). What we call main frequency 100MHz refers to this clock signal. 1/FCLK is the clock cycle of CPU.

PCLK is the clock signal provided for APB bus, which is mainly used for low-speed peripherals such as watchdog, UART controller, IIS, I2C, SDI/MMC, GPIO,RTC and SPI and so on.

3 configuration considerations

In the basic engineering, we use PLL as the system clock source, PLL is obtained by HSE frequency division, and the frequency division coefficient PLLM is 6. In order to ensure that the input frequency of VCO (voltage-controlled oscillator voltage controlled oscillator) is between 1 and 2MHz, it is recommended to choose 2MHz in order to limit PLL jitter. The important thing to pay attention to when configuring PLLN is to ensure that the output frequency of VCO is between 192 and 432MHz.

After reading the above, do you have any further understanding of the sample analysis of Clock Configration in STM32CubeMX? If you want to know more knowledge or related content, please follow the industry information channel, thank you for your support.

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