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What about the I2C deadlock?

2025-02-24 Update From: SLTechnology News&Howtos shulou NAV: SLTechnology News&Howtos > Internet Technology >

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This article is to share with you what to do about I2C deadlocks. The editor thinks it is very practical, so share it with you as a reference and follow the editor to have a look.

Reason

When the single-chip microcomputer is communicating with the I2C slave, if the master happens to send the 9th clock, the SCL is high, but pull down the SDA from the beginning to prepare for the low (as an ACK signal), wait for the master SCL to become low, and then release the SDA as high. If the MCU reset at this time, the master SCL has not yet had time to become low, directly become high, and the slave is still waiting for the SCL to become low, so the SDA; has been pulled down and the master has been found that the SDA has been low due to the reset, and is also waiting for the slave to release SDA as high. So both the master and the slave enter a deadlock state in which they wait for each other.

Solution.

The best method is to simulate i2c. However, because the hardware i2C has been configured, the program is changed to power on or reset to send 9 SCL clock signals to release SDA.

Try to choose the I2C slave device with reset input.

All the power supplies of the slave I2C devices are connected together and connected to the main power supply through the MOS tube, while the turn-on and off of the MOS tube is realized by the I2C master device.

In I2C, the function of watchdog is designed from the device.

Add the I2C bus recovery program to the I2C master device. After each reset of the I2C master device, if the SDA data line is detected to be pulled down, the SCL clock line in the I2C is controlled to generate 9 clock pulses (for 8-bit data), so that the I2C slave device can complete the suspended read operation and recover from the deadlock state. This method has great limitations, because most of the I2C modules of the main equipment are implemented by built-in hardware circuits, and the software can not directly control the SCL signal to simulate and generate clock pulses.

Add an additional bus recovery device to the I2C bus. This device monitors the I2C bus. When the device detects that the SDA signal is pulled down for more than a specified time, nine clock pulses are generated on the SCL bus, which makes the I2C read from the device and recover from the deadlock state. Bus recovery equipment needs to have programming function, which can be realized by single-chip microcomputer or CPLD.

String an I2C buffer with deadlock recovery on I2C. For example, Linear's LTC4307:LTC4307 is a bidirectional I2C bus buffer and has the function of I2C bus deadlock recovery. The LTC4307 bus input side connects the master device, and the bus output side connects all the slave devices. When LTC4307 detects that the SDA or SCL signal of the output side is pulled down the 30ms, it automatically disconnects the connection between the input side and the output side of the I2C bus. And 16 clock pulses are generated on the output side SCL signal to release the bus. When the bus is successfully restored, the LTC4307 will connect the input output side again, so that the bus can work properly.

Thank you for reading! This is the end of this article on "what to do with I2C deadlock". I hope the above content can be of some help to you, so that you can learn more knowledge. if you think the article is good, you can share it out for more people to see!

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