Shulou(Shulou.com)06/01 Report--

In this issue, the editor will bring you what DRC is like in the implementation of digital circuits. The article is rich in content and analyzes and describes for you from a professional point of view. I hope you can get something after reading this article.

Digital realization of silicon agriculture direction can be divided into front-end back-end or middle-end back-end, and then subdivision can be divided into synthesis, DFT, formal verification, PR, PV, PI, STA, etc., after subdivision, each type of work sewing buttons, hanging collar hanging collar, there are differences between each other, but no matter which type of work, will involve a word called DRC: Design Rule Check.

Timing related DRC

Max/min Transition time: used to constrain the maximum or minimum time allowed for the rising or falling process when the signal is flipped. In the implementation of the digital circuit, this value can be read from library or set with the command set_max_transition, set_min_transition. If both values exist at the same time, the tool takes the tightest benchmark when optimizing or checking.

As shown in the following example, there is usually a definition of default_max_transition in library, max_transition and min_transition on pin, and max_transition and min_transition in advanced process lib may be an one-dimensional or two-dimensional table.

Max/Min Capcitance: defines the maximum and minimum capacitive loads that cell inout or output port can drive. During the implementation of a digital circuit, this value can be read from library or defined by the command set_max_capacitance, set_min_capcitance. Usually, the value set by the command should not be greater than the value defined in library. Similarly, there is usually the definition of default_max_capacitance in library, max_capacitance and min_capacitance on pin, max_capacitance and min_capacitance in advanced technology lib may be an one-dimensional or two-dimensional table, the following example is an one-dimensional table index is frequency and a two-dimensional table index is frequency and transition.

Max/Min Fanout: there is usually a definition of fanout in the lib of the old process, but there is usually no definition of fanout in the library of the new process, so the tool will report an undefined warning when the tool parses the library, and the command set_max_fanout/ set_min_fanout is usually used to constrain the implementation process. It is said that in the advanced process node, as long as the max transition and max capcitance are repaired, max_fanout is not a hard rule that must be followed.

Physical related DRC

Both Placement and Routing have a lot of rule. Placement's rule specifies who can put together with whom, who can't, and how far it takes to avoid rubbing, removing sparks or biting each other. Routing's rule specifies the width, thickness, height and distance between the metal line and the through hole. There are roughly the following types:

The number of Minimum width and spacing for metalMinimum width and spacing for viaFat wire Via keep out EnclosureEnd of Line spacingMinimum areaOver Max stack levelWide metal jogMisaligned Via wireDifferent net spacingSpecial notch spacingShorts violationDifferent net Via cut spacingLess than min edge lengthPhysical DRC has been skyrocketing with the progress of the process nodes, which shows the complexity and difficulty of the manufacturing process, so all the costs are reasonable.

DFT-related DRC with the progress of technology, the special requirements of complex application scenarios are diversified, DFT is becoming more and more complex, and there are more and more rule. The most commonly involved DFT DRC includes the following parts:

This is what the DRC in the digital circuit implementation is like. If you happen to have similar doubts, you might as well refer to the above analysis to understand. If you want to know more about it, you are welcome to follow the industry information channel.

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