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This article is to share with you about the use of FIFO IP core notes, the editor feels very practical, so share with you to learn, I hope you can learn something after reading this article, do not say much, follow the editor to have a look.

Preface

FIFO? Or FIFO IP core? Does this also need to write a summary? It's too easy. If I were a young man who was interviewing for a job, I would be concerned about how to tear FIFO by hand, which is what I did in school recruitment at that time. But as FPGA engineers, we more often use FIFO's IP core, or inevitably use FIFO IP core, which is simple and quick to optimize. When using FIFO IP core, or when designing circuits using FIFO IP, for beginners or not proficient in the case, personal advice is to customize their own FIFO simulation (or strictly follow the data manual), so that the timing relationship is clear, then design the circuit. Note: don't disdain for this!

Here are a few notes on the use of FIFO IP core, where you want to go!

Bit width conversion FIFO of distributed ram resources cannot transform bit width

Block RAM resources can change the bit width

Builtin FIFO resources cannot change their bit width

FIFO safety circuit

There is an Enable Safety Circuit on the FIFO customization page, as follows:

Select this option and there are two additional output signals:

If you do not select Enable Safety Circuit, these two signal outputs do not exist:

This option is only customized for FIFO based on Bram resources, and cannot be selected if distributed RAM resources are used:

Similarly, the FIFO of the Builtin FIFO resource is not selectable.

If you are using the FIFO of this Block RAM resource, what is the use of selecting this signal? What do the two extra signals mean? What's the use? The author once made a mistake in the simulation, that is, several clocks after the reset are directly enabled to write, but no matter how to write the data, later found that the wr_rst_busy is in a high-level state, naturally can not be written. Therefore, if it is judged that the write enable is valid, the signal can be used as one of the judgment conditions, and if the signal is high, it cannot be written.

That raises a question? Since there is such a problem, how long will it take to write data to FIFO? That depends on how long after the reset is invalid before the signal can be pulled down, and the simulation shows that after about 20 clock cycles, the signal is pulled down and invalid. Will this affect our use of FIFO? You can imagine more than 20 clocks for how long, cycle ns level, and write enable can use this signal as a write enable valid condition, so it is easy to avoid this problem, the reason listed here is for simulation, if encountered can not be written into the situation, consider this problem, in order to avoid inexplicable, puzzled.

Xilinx also has a suggestion on the use of security circuits, that is, when asynchronous reset is selected, it may lead to damage to BRAM data, so it is recommended to use security circuits.

For asynchronous FIFO, it seems that asynchronous resets can only be used, which is all the more necessary.

FIFO consumes resources

Custom FIFO consumes resources related to what resources are used to generate FIFO. FIFO for Block RAM resources naturally uses Block RAM resources. There are two sizes of 7 series Block RAM resources used to generate FIFO, 18Kbit and 36Kbit. The general default bit is 18K and 36K.

If the FIFO bit width multiplication depth is less than 18K, naturally an 18K Bram is used, as follows:

Use Block RAM resources:

Nature greater than 18K is a 36KBlock RAM:

Use BRAM resources:

Greater than 36K, the situation is changeable, which is a combination of 18K and 36K:

The meaning of output delay Read Latency of 1

FIFO using distributed RAM resources and Block RAM resources can choose the output register to beat once, so that the natural Read Latency is 2, and it is impossible to select the output register to beat with Builtin FIFO resources.

If there is no register output, that is, the output does not store a beat, then what exactly does Read Latency = 1 mean here? I think the sequence chart speaks for itself best:

Take a look at the actual simulation: FIFO IP generates a summary:

Therefore, if you need to use rd_data data, you need to delay the read enable by one beat and use the actual value of the read data when judging the validity of the rd_en_r1:

The meaning that Read Latency is 2

Knowing the meaning that Read Latency is 1, it is easy to understand when it is 2. When adding register output, it will make Read Latency 2, as follows:

Under the same simulation:

The meaning of FIFO read-write counter

There are the following choices on the FIFO customization page: what do you mean by the two choices of Write Data Count,Read Data Count?

Let's write in a piece of data and look at the changes in the two data:

Write counter

Since the write count is valid, delay a clock and update the counter value to 1, which means that a data has been written; note: before we actually use the FIFO output parameters, we must simulate the timing relationship to prevent misuse.

Let's try to write two pieces of data to verify this relationship:

The relationship is consistent.

Read counter

The meaning of read counter is how much data is stored in FIFO? However, it will take some time to update this data, for example:

Updating the data requires at least four read clock cycles, so we cannot use this data immediately after it is written; this delay is the result of an asynchronous FIFO's internal clock domain.

Note: when using the internal output signal of the FIFO IP core, to be on the safe side, you need to simulate yourself and understand the timing relationship before designing the circuit.

For example, if two pieces of data are written, and then one is read out, the value must eventually be 1.

The result is verified by simulation.

All these situations mentioned above are actually reflected in the data manual, but for a FIFO, we all tend to use it directly and disdain to read the data manual. I have to say that this is a sign of youth or talent.

Therefore, for this case, we have two choices: one is to look at the data manual; the other is to simulate our own customized IP core and design the circuit after seeing the timing.

The above are the matters needing attention in the use of FIFO IP core, and the editor believes that there are some knowledge points that we may see or use in our daily work. I hope you can learn more from this article. For more details, please follow the industry information channel.

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