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This article introduces how the TMS320C6678 processor carries on the OpenMP multi-core communication case, the content is very detailed, the interested friends can refer to, hope to be helpful to everyone.

How to use TMS320C6678 processor for OpenMP multi-core communication case

The following mainly introduces the multi-core communication method commonly used in TMS320C6678 processor development: OpenMP, mainly based on Chuanglong Technology TL6678-EasyEVM evaluation board for demonstration.

Figure 1 TL6678-EasyEVM evaluation board

TL6678-EasyEVM is a high-end multi-core DSP evaluation board based on TI KeyStone architecture C6000 series TMS320C6678 8-core C66x fixed-point / floating-point high-performance processor, which is composed of core board and backplane. The core board has been verified by professional PCB Layout and high and low temperature tests, it is stable and reliable, and can meet a variety of industrial application environments.

The evaluation board is rich in interface resources, which leads to two-way gigabit network ports, SRIO, PCIe and other high-speed communication interfaces, which is convenient for users to quickly carry out product scheme evaluation and technical pre-research.

The development cases mainly include:

(1) bare metal development case

(2) RTOS (SYS/BIOS) development case

(3) Multi-core development cases of IPC and OpenMP

(4) Development cases of SRIO, PCIe and double Gigabit network ports

(5) Image processing development case

(6) the development case of DSP algorithm

(7) the development case of serial port and network remote upgrade.

Case source code, product materials (user manual, core board hardware materials, product specifications) can be obtained by site.tronlong.com/pfdownload.

2.1 introduction to OpenMP

OpenMP is a multi-core development software framework with the following main features:

(1) it can be used across platforms and has strong code compatibility.

(2) based on shared memory.

(3) support CCompact + and Fortran language.

(4) it is generally based on SYS/BIOS.

Figure 2

2.2 basic grammar

# pragma omp instruction [clause [,] clause].]

{

...

}

Table 1

Instruction

Description

Parallel

Start parallel execution of statements

For

Execute for loops in parallel in multiple threads

Sections

Contains multiple sectone structures that can be executed in parallel

Single

Single thread execution

Master

Main thread execution

Critical

Can only be executed by a single thread at any time

Barrier

Specify a barrier to synchronize all threads

Taskwait

Wait for the child thread to complete

Atomic

Make sure to specify the memory location to perform the atomic update operation

Flush

Make the current memory data of the thread consistent with the actual memory data

Ordered

For loops executed in parallel will be executed in the order of loop body variables

Threadprivate

Specifies that the variable is stored locally

Table 2

Clause

Description

Default

Controls the shared properties of variable data in a parallel or task structure

Shared

In a parallel or task structure, one or more variables are shared variables

Private

One or more variables are local variables

Firstprivate

One or more variables are local, and the value of the variable is the value before the execution of the parallel structure.

Lastprivate

One or more variables are local variables, and the value of the variable is the value after the parallel structure is executed.

Reduction

One or more variables are local, but the value of the variable will be determined according to different operators, and the value of the variable will be updated after execution is complete.

Copyin

Make the thread local variable value the same as the main thread variable value

Copyprivate

Make the values of variables that belong to the parallel region the same in different threads

Schedule

Set the parallel execution mode of for loop: dynamic, guided, runtime and static

Num_threads

Number of threads

If

Parallel statement execution condition

Nowait

Ignore thread synchronization wait

Take the bare metal omp_matavec case as an example, the summary flow chart of the usage scenario is as follows.

The C66xx_0 core creates the main thread, and loads the matvec algorithm to the C66xx_0~C66xx_7 core for parallel operation through the OpenMP framework, thus reducing the load of the C66xx_0 core and speeding up the operation speed.

Now you can apply for TL6678-EasyEVM evaluation board for quick assessment free of charge to the manufacturer. Technical seminars: 79635273, 332643352

Figure 3

2.3 Code Analysis

Take the bare metal omp_matavec case as an example for code analysis, as noted in the figure.

Figure 4

On how the TMS320C6678 processor OpenMP multi-core communication case is shared here, I hope the above content can be of some help to you, can learn more knowledge. If you think the article is good, you can share it for more people to see.

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