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This article will explain in detail how to deal with CDC cross-clock domain and the corresponding timing constraints. The content of the article is of high quality, so the editor will share it for you as a reference. I hope you will have a certain understanding of the relevant knowledge after reading this article.

Multi-bit cross-clock domain

(Dajiang 2020 digital chip) the following ideas about the processing of multi-bit data across clock domain, the errors are ()

a. The sender gives the data, and the receiver synchronizes two beats with the local clock before using it.

b. The sender writes the data to the asynchronous fifo and the receiver reads it from the asynchronous fifo.

c. For continuously changing signals, the sender transmits the Gray code, and the receiver receives it and then converts it to binary.

d. The sender gives the data, the sender gives the handshake request, the receiver replies after receiving it, and the sender cancels the data.

Answer: a

Analysis: multi-bit cross-clock domain can not be simply used to hit two beats, after hitting the data may be out of order

CDC (Clock Domain Conversion) is divided into single bit and multi-bit transmissions across clock domains, where:

1. Single bit (slow clock domain to fast clock domain): use the fast clock to hit two beats, and directly take one beat with high probability. The main purpose of the two beats is to eliminate metastability.

Where:

The main results are as follows: (1) in order to achieve a longer mean time between failures (Mean Time Between Failures), it is necessary to cooperate with the constraint of an ASYNC_REG to put multiple registers used as a simple synchronizer into the same SLICE to reduce the inconsistency and uncertainty of routing delay.

(* ASYNC_REG = "TRUE" *) reg rst_reg_0; (* ASYNC_REG = "TRUE" *) reg rst_reg_1

(2) or: constrain directly in the constraint file

Set_property ASYNC_REG TRUE [get_cells [list rst_reg_0 rst_reg_1]]

two。 Single bit (fast clock domain to slow clock domain): the pulse width of the fast clock domain of handshake (pulse broadening), asynchronous FIFO and asynchronous dual-port RAM; is narrow, and the slow clock domain may not be collected. The narrow pulse can be broadened by the handshake mechanism. After the signal is collected in the slow clock domain, it is "told" that the signal has been collected in the fast clock domain to ensure that it can be collected.

3. Multi-bit cross-clock domain: asynchronous FIFO, asynchronous dual-port RAM, handshake, Gray code

(1) IP using asynchronous FIFO

In fact, it is built with BRAM within FPGA, and all the control logic is within BRAM, which is the recommended implementation of FIFO.

Timing constraint is simple, timing exception constraint, only need set_clock_groups to restrict the read and write clock to asynchronous clock group, simple and efficient.

Set_property-asynchronous-group [get_clocks write_clock]\-group [get_clocks read_clock]

(2) write the FIFO of external control logic yourself.

Gray code does the cross-clock domain processing of asynchronous FIFO. Counters and read-write control logic are outside of BRAM or RAM. In addition to the reasonable design of the code, additional timing exception constraints are needed. We can not simply use set_clock_groups to constrain asynchronous clock groups, but also need to consider external read-write logic constraints.

Xilinx recommends that set_max_delay be set here to constrain the path across the clock domain. The principle of the constraint is that the maximum path delay is equal to or slightly less than one cycle of the destination clock.

In the write logic constraint from cell1 to cell2, the drive clock cycle of cell2 is 5, as shown below, and the read logic constraint is constrained accordingly.

Set_max_delay 5-from [get_cells cell1]-to [get_cells cell2]-datapath_only

In multi-bit, it is highly recommended to use the IP of asynchronous FIFO. I use it many times in practical projects, which is simple and convenient.

On how to carry out CDC cross-clock domain processing and the corresponding timing constraints to share here, I hope that the above content can be of some help to you, can learn more knowledge. If you think the article is good, you can share it for more people to see.

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