Shulou(Shulou.com)06/01 Report--

In this issue, the editor will bring you about the Verilog HDL implementation of the CRC16 encoder. The article is rich in content and analyzes and describes for you from a professional point of view. I hope you can get something after reading this article.

The generating polynomial used in CRC-16 code is

G (x) = x16 + x15 + x2 + 1

Module crc_16 (

Clk,rst,x,crc_reg,crc_s

);

Input clk

Input rst

Input XTX Universe serial input

Output [15:0] crc_reg

Output crc_s;//the synchronous signal

Reg [15:0] crc_reg

Reg [3:0] count

Reg crc_s

Wire [15:0] crc_enc

Always @ (posedge clk)

Begin

If (! rst)

Begin

Crc_reg

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