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The concept of variables in the programming language is supported in makefile, and variables in makefile only represent text data (strings). So what are the rules for variable names in makefile? A > variable names can contain characters, numbers, and underscores; b > cannot contain ":", "#", "=" or "; c > variable names are case-sensitive. Let's take a look at the definition and use of variables, as follows

Let's take the code as an example to analyze and illustrate.

CC: = gccTARGET: = hello.out$ (TARGET): func.o main.o $(CC)-o $(TARGET) func.o main.ofunc.o: func.c $(CC)-ofunc.o-c func.cmain.o: main.c $(CC)-o main.o-c main.c.PHONY: rebuild clean allrebuild: clean allall: $(TARGET) clean: rm * .o $(TARGET)

Let's see if the compilation result is the same as before.

The effect is the same as before, so why do we define variables in this way? In some large engineering projects, we may have to compile several versions, so different TARGET definitions will compile different versions. And another advantage of this method is that the compiler can be customized by us. For example, if we replace the above gcc compiler with CC: = gcc, we just need to replace it with CC: = glossy compiler. Let's take a look at the compilation effect.

We see that the compiler has been changed to glossy +. Let's talk about the assignment of variables in makefile, which can be divided into four ways: a > simple assignment (: =); b > recursive assignment (=); c > conditional assignment (? =); d > additional assignment (+ =). Then the meaning of different assignment methods is different! Next, let's explain these four assignment methods one by one.

A > simple assignment (: =): a common assignment in a programming language that is valid only for variables in the current statement. Its usage is as follows

B > Recursive assignment (=): the assignment operation may affect multiple other variables, and all other variables related to the target variable will be affected. Its usage is as follows

C > conditional assignment (? =): if the variable is not defined, the value in the assignment symbol is used to define the variable; if the variable is already defined, the assignment is invalid. Its usage is as follows

D > append assignment (+ =): add a new value after the original variable value, and the original variable value is separated from the new value by a space. Its usage is as follows

Let's take the code as an example.

# ex1 (: =) x: = fooy: = $(x) bx: = new.PHONY: testtest: @ echo "# ex1 (: =)" @ echo "x = > $(x)" @ echo "y = > $(y)"

After a simple assignment, x is new and y should be foob. Let's take a look at the compilation effect.

We see that the result is the same as what we analyzed. Let's take a look at recursive assignment.

# ex2 (=) x = fooy = $(x) bx = new.PHONY: testtest: @ echo "# ex2 (=)" @ echo "x = > $(x)" @ echo "y = > $(y)"

Let's analyze, because the recursive assignment is that other variables related to the target will be affected, then x should finally be new,y should be newb. Let's take a look at the compilation results.

To illustrate recursive assignment more vividly, we write the following code

A = $(b) b = $(c) c = hello-makefile.PHONY: testtest: @ echo "# ex2 (=)" @ echo "x = > $(x)" @ echo "y = > $(y)" @ echo "a = > $(a)" @ echo "b = > $(b)" @ echo "c = > $(c)"

We define that a depends on b and b depends on c. When c is hello-makefile, the b that depends on it becomes hello-makefile, and the a that depends on b becomes hello-makefile. X and y are not defined at this time. Will the compilation report an error?

Compilation is passed, proving that such writing is supported in makefile, and that x and y are not defined, so they are naturally empty. So a _ r _ r _ b _ c is the same as what we analyzed. So we rarely use recursive assignment directly in makefile, because it is possible to unexpectedly change the goal that depends on it. Let's take a look at conditional assignment.

# ex3 (?) x: = fooy: = $(x) bx? = new.PHONY: testtest: @ echo "# ex3 (?)" @ echo "x = > $(x)" @ echo "y = > $(y)"

We end up with x? = new, which means that if it's not defined before, it's new. So x should finally be foo,y and it should be foob. Let's take a look at the compilation results.

The result is that we usually use this method when we newly define variables to prevent the semantics of the previous definition from being changed. Finally, take a look at the additional assignment.

# ex4 (+ =) x: = fooy: = $(x) bx + = new.PHONY: testtest: @ echo "# ex4 (+ =)" @ echo "x = > $(x)" @ echo "y = > $(y)"

According to the definition of the append assignment, it is added directly to the end, but there is a space. So x should finally be foo new,y and it should be foob. Let's take a look at the compilation results.

We understand that the effect is indeed like this. Through the study of the four assignment methods, we find that the simple assignment is the same as in C language. Additional assignment is the same as the semantics in C++ language, and recursive assignment is not commonly used in large projects.

Welcome to learn makefile, you can add me QQ:243343083.

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