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This article mainly introduces an example analysis of the working mechanism of make commands in Linux, which has a certain reference value, and interested friends can refer to it. I hope you will gain a lot after reading this article.

The make command under Linux is one of the most frequently used commands for system administrators and programmers. Administrators use it to compile and install many open source tools from the command line, and programmers use it to manage their large and complex project compilation problems.

For those who don't know the mechanism behind it, the make command receives the target like a command-line argument. These targets are usually stored in a special file named "Makefile", which also contains actions corresponding to the target. For more information, read a series of articles on how Makefiles works.

When the make command is executed for the first time, it scans the Makefile for the target and its dependencies. If these dependencies are targets themselves, continue to establish their dependencies for the scan Makefile for these dependencies, and then compile them. Once the primary dependency has been compiled, the primary target is then compiled (which is passed in through the make command).

Now, suppose you make changes to a source file, and you execute the make command again, which will compile only the target files associated with that source file, so compiling the final executable saves a lot of time.

How does Make work

The following is the test environment used in this article:

OS-Ubunut 13.04Shell-Bash 4.2.45Application-GNU Make 3.81

The following is the content of the project:

$lsanotherTest.c Makefile test.c test.h

Here is the content of Makefile:

All: testtest: test.o anotherTest.o gcc-Wall test.o anotherTest.o-o testtest.o: test.c gcc-c-Wall test.canotherTest.o: anotherTest.c gcc-c-Wall anotherTest.cclean: rm-rf * .o test

Now let's look at some examples of the application of make commands under Linux:

1. A simple example.

To compile the entire project, you can simply use make or take the target all after the make command.

$makegcc-c-Wall test.cgcc-c-Wall anotherTest.cgcc-Wall test.o anotherTest.o-o test

You can see the dependencies created by the make command for the first time as well as the actual target.

If you look at the contents of the directory again, there are some .o files and execution files in it:

$lsanotherTest.c anotherTest.o Makefile test test.c test.h test.o

Now, suppose you make some changes to the test.c file and re-use make to compile the project:

$makegcc-c-Wall test.cgcc-Wall test.o anotherTest.o-o test

You can see that only test.o has been recompiled, while another Test.o has not been recompiled.

Now clean up all the target files and executable test, you can use the target clean:

$make cleanrm-rf * .o test$ lsanotherTest.c Makefile test.c test.h

You can see that all .o files and executable test have been deleted.

two。 Make all targets always re-established with the-B option

So far, you may have noticed that the make command does not compile files that have not changed since the last compilation, but if you want to override the default behavior of make, you can use the-B option.

Here is an example:

$makemake: Nothing to be done for `all'.$ make-Bgcc-c-Wall test.cgcc-c-Wall anotherTest.cgcc-Wall test.o anotherTest.o-o test

You can see that although the make command does not compile any files, make-B forces the compilation of all target files and the final execution file.

3. Use the-d option to print debugging information

If you want to know what make actually does during execution, use the-d option.

This is an example:

$make-d | moreGNU Make 3.81Copyright (C) 2006 Free Software Foundation, Inc.This is free software; see the source for copying conditions.There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR APARTICULAR PURPOSE.This program built for x86_64-pc-linux-gnuReading makefiles... Reading makefile `Makefile'... Updating makefiles... .Considering target file `Makefile'.Looking for an implicit rule for `Makefile'.Trying pattern rule with stem `Makefile'.Trying implicit prerequisite `Makefile.o'.Trying pattern rule with stem `Makefile.c'.Trying pattern rule with stem `Makefile'.Trying implicit prerequisite `Makefile.cc'.Trying pattern rule with stem `Makefile'.Trying implicit prerequisite `Makefile'.Trying implicit prerequisite `Makefile.cpp'.Trying pattern rule with stem `Makefile'.--More--

This is a long output, and you can see that I used the more command to display the output page by page.

4. Use the-C option to change the directory

You can provide different directory paths for the make command, and you will change directories before looking for Makefile.

This is a directory, assuming you are in the current directory:

$lsfile file2 frnd frnd1.cpp log1.txt log3.txt log5.txtfile1 file name with spaces frnd1 frnd.cpp log2.txt log4.txt

But the Makefile file of the make command you want to run is saved in the.. / make-dir/ directory, you can do this:

$make- C.. / make-dir/make: Entering directory `/ home/himanshu/practice/make-dir'make: Nothing to be done for `all'.make: Leaving directory` / home/himanshu/practice/make-dir

You can see that the make command is first cut to a specific directory, executed there, and then switched back.

5. Treat other files as Makefile with the-f option

If you want to rename the Makefile file, such as my_makefile or something else, we want make to think of it as Makefile, using the-f option.

Make-f my_makefile

In this way, the make command chooses to scan my_makefile instead of Makefile.

Thank you for reading this article carefully. I hope the article "sample Analysis of the working Mechanism of make commands in Linux" shared by the editor will be helpful to you. At the same time, I also hope that you will support and pay attention to the industry information channel. More related knowledge is waiting for you to learn!

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