Shulou(Shulou.com)06/02 Report--

 The memory controller of the S3C2440 provides the signals needed to access peripherals, and it has the following characteristics:

Support for large/small endian bytes (selected by software); address space of 128MB per BANK for a total of 1GB(8 BANKs); programmable bus width (8/16/32bit), BANK0 has only two bits wide (16/32bit); a total of 8 BANK: BANK0-BANK5 can support external ROM, SRAM, etc.;BANK6-BANK7 in addition to support ROM, SRAM, but also support SDRAM, etc.;BANK0-BANK6 seven BANK start address fixed;BANK7 start address programmable selection; each BANK access cycle programmable control; Extend bus access cycle by external wait signal; support self-refresh and power-saving mode when external SDRAM.

 The access range of 27 address lines ADDR0-ADDR26 led out by S3C2440 is only 128MB, while the eight chip select signals nGCS0-nGCS7 correspond to BANK0-BANK7. When accessing the address space of BANKx, the nGCSx pin outputs low level to select the external device. Each nGCSx corresponds to 128MB of address space, and the eight nGCSx signals correspond to a total of 1 GB.

 BANK6 in the TQ2440 board connects to SDRAM, to which the CPU provides a set of signals for SDRAM:

SDRAM clock valid signal LSCKE;SDRAM clock signals LSCLK0/LSCLK1; data mask signals LnWBE0/LnWBE1/LnWBE2/LnWBE3;SDRAM row address strobe signal LnSRAS;SDRAM column address strobe signal LnSCAS; write enable signal LnWE

1, SDRAM introduction

 Inside SDRAM is a memory array, like a two-dimensional table, into which data is filled. The retrieval principle is the same as the table, first specify a row address, and then specify a column address to accurately find the required cells. This cell is called a memory cell, and the table is called a logical BANK(L-BANK), SDRAM generally has four L-BANK logic diagram as shown in the figure above.

 Access to SDRAM can be divided into four steps:

1. Chip selection signal LnSCS0 sent by CPU is valid;2. There are 4 L-BANK in SDRAM, and two address lines are needed to select one of them. It can be seen from the figure that ADDR24 and ADDR25 are used as L-BANK selection signals;3. Unified row/column (memory unit) addressing is carried out on the selected chip;4. After the memory unit is found, the selected chip carries out the same data transmission.

 In the TQ2440 development board, two 16-bit ADRAM chips are used in parallel to form a 32-bit width, which is connected to 32 data lines (DATA0-DATA31) of the CPU. BANK6 starts at 0x3000000, so SDRAM access addresses are 0x3000000-ox33ffffff, for a total of 64MB.

2. Register usage of memory controller

 In S3C2440, the memory controller has 13 registers in total. BANK0-BANK5 only needs to set BWSCON and BANKCONx(x is 0-5). When BANK6/BANK7 is externally connected to SDRAM, besides WSCON and BANKCONx(x is 6-7), REFRESH, BANKSIZE, MRSRB6, MRSRB7 and other four registers need to be set. Each register is described separately below.

Bit Width and Wait Control Register BWSCON

BWSCON Description STx enables/disables SDRAM data mask pin, 0 for SDRAM; 1 for SRAM WSx whether to use WAIT signal of memory, usually set to 0DWx uses two bits to set the bit width of corresponding BANK, 0 b00 corresponds to 8 bits, 0 b01 corresponds to 16 bits, 0b10 corresponds to 32 bits, 0b11 is reserved

 For BANK0, it does not have ST0 and WS0, DW0([2:1]), bank0 only supports two bit widths 16/32.

BANK control register BANKCONx(x is 0-5), which controls the access timing of BANK0-BANK5 external devices. The default 0x0700 can meet the requirements of TQ2440 development board.

BANK control register BANKCONx(x is 6-7). Among the 8 BANKs, only BANK6 and BANK7 can be externally connected to SRAM or SDRAM, so their setting methods are different.

BANKCONn Description MT [16:15] is used to set BANK external SRAM or SDRAM, 00 = ROM or SRAM, 11 = Sync. DRAMTrcd [3:2]RAS to CAS delay, recommended setting 0b 01SCAN [1:0]SDRAM column address bits, 00 = 8-bit 01 = 9-bit 10= 10-bit

Refresh Control Register REFRESH

REFRESH Description REFEN [23]0, disable SDRAM refresh function, 1, enable SDRAM refresh function REFMD [22]SDRAM refresh mode. 0 = CBR/Auto Refresh 1 = Self Refresh Trp [21:20] Normally set to 0Tsrc [19:18] Set to default 11Refresh Counter [10:0] Refresh value for SDRAM, Refresh period = (211-SDRAM clock frequency (MHX)+1)/sdram refresh period (us)

BANKSIZE register

BANKSIZE Description BURST_EN [7]0, disable ARM core burst transfer;1, ARM core supports burst transfer SCKE_EN [5]0, do not use SCKE signal to put SDRAM into power saving mode;1, use SCKE signal to put SDRAM into power saving mode SCLK_EN [4]0, issue SCLK signal at all times;1, issue SCLE signal BK76 MAP [2:0] only during SDRAM access Configure BANK size

SDRAM mode setting register MRSRBx (6-7)

MRSRBx Description CL [6:4]SDRAM timing time parameter settings

3. Memory controller experiment; light LED lamp

 When booting the CPU from NAND Flash, the CPU copies the 4KB data starting with NAND Flash to the 4KB internal RAM called Steppingstone (starting at address 0) through internal hardware, and then jumps to address 0 to start execution.

 This experiment uses assembly language to set up memory controller first, make external SDRAM available, then copy the program itself from Steppingstone to SDRAM, and finally jump to SDRAM execution.

First in the head.S file, the job done is to set up SDRAM, copy the program to SDRAM, and then jump to SDRAM to continue execution.

.equ MEM_CTL_BASE, 0x48000000.equ SDRAM_BASE, 0x30000000.text.global _start_start: bl disable_watch_dog @ Turn off WATCHDOG, otherwise the CPU will keep restarting. bl memsetup @ Set Storage Controller bl copy_steppingstone_to_sdram @ Copy code to SDRAM ldr pc, =on_sdram @ Jump to SDRAM and continue on_sdram: ldr sp, =0x34000000 @ Settings Stack bl mainhalt_loop: b halt_loopdisable_watch_dog: @ Write 0 to WATCHDOG register mov r1, #0x53000000 mov r2, #0x0 str r2, [r1] mov pc, lr @ Return copy_steppingstone_to_sdram: @ Copy Steppingstone's 4K data to SDRAM @ Steppingstone starts at 0x000000, SDRAM starts at 0x3000000 mov r1, #0 ldr r2, =SDRAM_BASE mov r3, #4*10241: ldr r4, [r1],#4 @ Read 4 bytes of data from Steppingstone and increment the source address by 4 str r4, [r2],#4 @ Copy this 4-byte data to SDRAM and increment the destination address by 4 cmp r1, r3 @ Judge whether it is complete: source address equal to unaddressed address of Steppingstone? bne 1b @ If not copied, continue mov pc, lr @ Back to memsetup: @ Set up the memory controller to use peripherals such as SDRAM mov r1, #MEM_CTL_BASE @ Start address of 13 registers of memory controller adrl r2, mem_cfg_val @ The starting storage address of these 13 values add r3, r1, #52 @ 13*4 = 541: ldr r4, [r2], #4 @ Read the settings and add 4 to r2 str r4, [r1], #4 @ Write this value to the register and add 4 to r1 cmp r1, r3 @ Determine if all 13 registers have been set bne 1b @ If not written, continue mov pc, lr @ Back to.align 4mem_cfg_val: @ Store settings for 13 registers of controller .long 0x22011110 @ BWSCON .long 0x00000700 @ BANKCON0 .long 0x00000700 @ BANKCON1 .long 0x00000700 @ BANKCON2 .long 0x00000700 @ BANKCON3 .long 0x00000700 @ BANKCON4 .long 0x00000700 @ BANKCON5 .long 0x00018005 @ BANKCON6 .long 0x00018005 @ BANKCON7 .long 0x008C07A3 @ REFRESH .long 0x000000B1 @ BANKSIZE .long 0x00000030 @ MRSRB6 .long 0x00000030 @ MRSRB7

In the leds.c file, complete the led cycle flashing experiment:

#define GPBCON (*(volatile unsigned long *)0x56000010)#define GPBDAT (*(volatile unsigned long *) 0x56000014)/* * LED1,LED2,LED4 for GPB5, GPB6, GPB7, GPB8 */#define GPB5_out (1

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