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This article will explain what STM32 DAC is for you in detail. The editor thinks it is very practical, so I share it with you as a reference. I hope you can get something after reading this article.

Since there is an analog-to-digital ADC module, there must be a digital-to-analog DAC module. As the name implies, this module only has the complementary functions of ADC. It converts digital binary values into analog voltage output. DAC module has a variety of uses, including audio generation, waveform generation and so on. Usually in most 8-bit microcontrollers, this module is not available and can be slightly satisfied by pulse width modulation (PWM). This is partly due to their relatively low hardware resources and running speed. All STM32 microcontrollers have PWM module, but large-capacity STM32 also has DAC module. The STM32DAC module is not very complex and is similar to the ADC module in working principle.

01. Introduction to DAC

As you can see from the STM32F207 data manual, STM32F207 has two DAC modules.

Each DAC has its own channel, and the corresponding GPIO are: PA4 and PA5. For the reuse function (Alternatefunctions) and additional function (Additionalfunctions) of GPIO, it is explained in detail in "STM32ADC detailed explanation".

In addition to the DAC output pin, there are other related pins

Note: when DAC channel x is enabled, the corresponding GPIO pin (PA4 or PA5) will be automatically connected to the analog converter output (DAC_OUTx). To avoid parasitic current consumption, the PA4 or PA5 pins should first be configured in analog mode (AIN).

The following simplified block diagram shows the main components of the STM32DAC module.

02, DAC conversion

As can be seen from the block diagram, DAC is directly controlled by the DORx register, but can not write data directly to the DORx register, but is indirectly transferred to the DORx register through DHRx to realize the output control of DAC.

You cannot write data directly to the register DAC_DORx, and any data output to DAC channel x must be written to the DAC_DHRx register (the data is actually written to the DAC_DHR8Rx, DAC_DHR12Lx, DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12LD, or DAC_DHR12RD registers).

If the hardware trigger is not selected (TENx position 0 of register DAC_CR1), the data stored in register DAC_DHRx is automatically transferred to register DAC_DORx after an APB1 clock cycle

If hardware trigger is selected (register TENx position 1 of DAC_CR1), the data transfer is completed three APB1 clock cycles after the trigger occurs.

Once the data is loaded from the DAC_DHRx register into the DAC_DORx register, the output is valid after the time tSETTLING, which varies according to the power supply voltage and the analog output load.

DAC control register (DAC_CR)

DMAEN1:DAC channel 1DMA enable (DAC channel1 DMA enable), we do not use DMA, so set to 0

MAMP1 [3:0]: DAC Channel 1 Shield / amplitude Selector (DAC channel1 mask/amplitude selector) We didn't use it, so these bits are also set to 0

WAVE1 [1:0]: DAC Channel 1 noise / triangular Wave Generation enable (DAC channel1 noise/triangle wave generationenable) We didn't use it either, so it's set to 0.

TEN1:DAC channel 1 trigger enable (DAC channel1 trigger enable) We do not need to trigger, so set to 0

TSEL1 [2:0]: DAC Channel 1 trigger selection (DAC channel1 trigger selection) Note: this bit can only be set when TEN1=1 (DAC Channel 1 triggers enable). Our TEN1 is set to 0, so these bits do not need to be set. The default is 0.

BOFF1: turn off DAC channel 1 output cache (DAC channel1 output buffer disable) We turn off the output buffer and set it to 1

EN1:DAC channel 1 enable (DAC channel1 enable) We want to enable DAC channel, so it is set to 1.

03. Function description

The DAC equivalent circuit of STM32 is as follows

The output buffer shown in the circuit runs on an internal 3.3V power supply. As with most operational amplifiers running on a single power supply (rather than a + /-dual power supply), the output swing will never really reach the target. However, as shown in the circuit, there are two internal switches (S1 and S2) that can be controlled by registers. Turning them on will connect the "DACINT" signal directly to the "DACOUT" pin through two series resistors (Ra and Rb). For reference, the Ra+ Rb is about 15k.

Depending on the selected configuration mode, the data is written to the specified register as described below:

Single DAC channel x, there are 3 situations:

Right alignment of 8-bit data: the user must write the data to the register DAC_DHR8Rx [7:0] bit (actually in the register DHRx [11:4] bit)

Left alignment of 12-bit data: the user must write the data to the register DAC_DHR12Lx [15:4] bit (actually in the register DHRx [11:0] bit)

12-bit data right alignment: the user must write the data to the register DAC_DHR12Rx [11:0] bit (actually in the register DHRx [11:0] bit).

The third way is generally adopted: there is more right alignment of 12-bit data.

According to the operation on the DAC_DHRyyyx register, after the corresponding shift, the written data is transferred to the DHRx register (DHRx is the internal data storage register x). Subsequently, the contents of the DHRx register are either automatically transferred to the DORx register or via software trigger or external event trigger to the DORx register.

Dual DAC channels, there are 3 situations:

Right alignment of 8-bit data: the user must write DAC channel 1 data to register DAC_DHR8RD [7:0] bit (actually in register DHR1 [11:4] bit) and DAC channel 2 data to register DAC_DHR8RD [15:8] bit (actually in register DHR2 [11:4] bit).

12-bit data left alignment: the user must write DAC channel 1 data to the register DAC_DHR12LD [15:4] bit (actually in the register DHR1 [11:0] bit) and DAC channel 2 data to the register DAC_DHR12LD [31:20] bit (actually in the register DHR2 [11:0] bit)

12-bit data right alignment: the user must write DAC channel 1 data to the register DAC_DHR12RD [11:0] bit (actually in the register DHR1 [11:0] bit) and DAC channel 2 data to the register DAC_DHR12RD [27:16] bit (actually in the register DHR2 [11:0] bit).

04, DAC output voltage

When the reference voltage bit of DAC is VREF+, the digital input is linearly converted to analog voltage output through DAC, which ranges from 0 to VREF+.

The output voltage on any DAC channel pin satisfies the following relationship:

DAC output = VREF x (DOR / 4095).

Note: at this time the data format: 12-bit data right alignment should be selected.

05. Code configuration

DAC configuration

Void DAC1_Config (void) {DAC_InitTypeDef DAC_InitStructure; GPIO_InitTypeDef GPIO_InitStructure; / * DMA1 clock and GPIOA clock enable (to be used with DAC) * / RCC_AHB1PeriphClockCmd (RCC_AHB1Periph_GPIOA, ENABLE); / * DAC Periph clock enable * / RCC_APB1PeriphClockCmd (RCC_APB1Periph_DAC, ENABLE); / * DAC channel 1 & 2 (DAC_OUT1 = PA.4) (DAC_OUT2 = PA.5) configuration * / GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init (GPIOA, & GPIO_InitStructure); / * DAC channel2 Configuration * / DAC_InitStructure.DAC_Trigger = DAC_Trigger_None; DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None; DAC_InitStructure.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Disable DAC_Init (DAC_Channel_1, & DAC_InitStructure); / * Enable DAC Channel2 * / DAC_Cmd (DAC_Channel_1, ENABLE);}

Set output voltage

/ / set the output voltage of channel 1 / / vol:0~3300, representing 0~3.3Vvoid Dac1_Set_Vol (uint16_t vol) {double temp=vol; temp/=1000; temp=temp*4096/3.3; DAC_SetChannel1Data (DAC_Align_12b_R,temp); / / 12-bit right-aligned data format setting DAC value}

The test case is simple, which is to output 1.2V and 3.0V voltage repeatedly.

While (1) {GPIO_SetBits (GPIOE,GPIO_Pin_4); / / turn off LED light Dac1_Set_Vol (1200); LCD_ShowString (0L0, "DAC OUT 1.2V"); Delay (500V); / / delay 500ms GPIO_ResetBits (GPIOE,GPIO_Pin_4); / / turn on LED light Dac1_Set_Vol (3000); LCD_ShowString (0L0, "DAC OUT 3.0V") Delay; / / delay 500ms}

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