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This article mainly introduces "how to design an arbitrator with Verilog Basics". In daily operation, I believe many people have doubts about how to design an arbitrator with Verilog Basics. The editor consulted all kinds of materials and sorted out a simple and easy-to-use method of operation. I hope it will be helpful to answer the doubts of "how to design an arbitrator with Verilog Basics". Next, please follow the editor to study!

Introduction

Every Verilog beginner's dream is to understand it in one day, at least to the extent that it can be used. The next few articles from Verilog Basics will make this dream come true.

Although Verilog executes different blocks of code in parallel, it still has many similarities with most sequential programming languages. All we need is the basics of some digital circuits.

Before the advent of Verilog, circuit designers used schematics to design circuits. Regardless of the complexity, each design is designed through a schematic. This makes the design difficult to verify and error-prone, leading to the design. Verification, design. Verification, design. Verification, design. Validating... Tedious iterations.

When Verilog appeared, we had different ways of thinking about digital circuit design. The functional design cycle of digital circuits using Verilog is similar to the traditional program development cycle.

Specifications (specs)

High level design

Low level (micro) design

RTL coding

Verification

Synthesis.

First we need a specifications that lists our design restrictions (restrictions) and requirements (requirements)

In this tutorial, we will design an arbitrator (arbiter). Here are some specifications for the arbitrator.

Two agent

Asynchronous reset, high efficiency

Fixed priority, agent0 takes precedence over agent1

After we have the specification, we can draw a block diagram, that is, to design the black box of the data flow.

Block diagram of arbiter

If there is no Verilog, the next step is to start drawing the state machine. We make a truth table with state transition, then draw the Karnaugh map and simplify the optimization circuit.

Each circle represents the state in which the state may be. Each state has a corresponding output. The arrows between states are state transitions caused by different events.

For example, the leftmost orange arrow indicates that if the machine is in a GNT0 state (outputs a signal corresponding to GNT0) and receives it! The input of req_0, the state machine moves to the state IDLE and outputs the corresponding signal.

This design method is suitable for small designs, but for large designs, the process becomes complex and error-prone. This is the opportunity for Verilog to use his talents.

Modules

In the block diagram of the arbitration block, we can see that it has a name ("arbiter") and input / output ports (req_0,req_1,gnt_0 and gnt_1).

In Verilog, we use module to describe this black box with the same input and output.

This code is shown below.

Module arbiter (/ / Two slashes make a comment line.clock, / / clockreset, / / Active high, syn resetreq_0, / / Request 0req_1, / / Request 1gnt_0, / / Grant 0gnt_1 / / Grant 1); / /-Input Ports--// Note: all commands are semicolon-delimitedinput clock; input reset; input req_0; input req_1 / /-Output Ports--output gnt_0; output gnt_1

Data Type

There are two data types in hardware

1. The data type in which values can be stored (for example, flip-flop).

2. The data type of the value cannot be stored, but two points can be connected (for example: wire).

The first type is called reg (abbreviation for "register") in Verilog. The second data type is called wire ("wire").

For example:

Wire and_gate_output; reg dudes flipsticks floppy output reg [7:0] address_bus

Operators

The operators in Verilog are almost the same as in other programming languages.

Operator Type

Operator Symbol

Operation Performed

Arithmetic

*

Multiply

/

Division

+

Add

-

Subtract

%

Modulus

+

Unary plus

-

Unary minus

Logical

!

Logical negation

& &

Logical and

| | |

Logical or

Relational

>

Greater than

=

Greater than or equal

>

Right shift

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