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It is believed that many inexperienced people have no idea about how to combine ModelSim with Quarus automatic simulation. Therefore, this paper summarizes the causes and solutions of the problem. Through this article, I hope you can solve this problem.

The automatic simulation of ModelSim engineering practice has finished the process of using ModelSim, and then we will demonstrate the operation of each process in detail, leading you to learn to use ModelSim software step by step. First of all, we talk about ModelSim automatic simulation, the so-called automatic simulation, in fact, call ModelSim software in Quartus II to carry out simulation, in the process of calling, Quartus II will help us complete all the operations in ModelSim, we only need to analyze the final simulation results. Let's take the Quartus II software project we created in the above chapter as an example to simulate. Check the EDA path first we open the previous Quartus II project, as shown in the figure on this page, we find the [Tool] → [Options] button in the menu bar and open it. On the left side of the open page, we find "EDA Tool Options" and click, as shown in the figure on this page. If you are installing ModelSim software, then you need to set it in the ModelSim path. Here we use ModelSim-Altera. So we set the ModelSim-Altera path to C:\ altera\ 13.1\ modelsim_ase\ win32aloem. What you need to pay attention to here is that you must select win32aloem in the modelsim_ase folder, not win32aloem in the modelsim_ae folder. Remember what we said earlier? Ae is a paid version, we can't use it, and the free version of ase here can also satisfy our design. After the path is set, we click [OK] to return to our Quartus II software interface. Select EDA tool We find the [Assignments] → [Settings] button in the menu bar of the Quartus II software page and open it. On the left side of the open page, we find "EDA Tool Settings" and click, as shown in the figure.

Remember when we created the project before, because we didn't use simulation in Quartus II software, we set this to "None". Now we need to use simulation tools, and we need to set Simulation to "ModelSim-Altera, Verilog HDL" here. After the setup is complete, we click [OK] to return to the Quartus II software page. 0.3 write the simulation file in the menu bar of the Quartus II software page, we find the [Processing] → [Start] → [Start TestBench Template Writer] button and click it, which will be displayed in the Message window, as shown in the figure.

We can know from this message that Quartus II software automatically generates a TestBench template for us, and we only need to modify this template to use it directly. We found the Verilog_First.vt file in the project directory, we can use notepad to open it for modification, we can also use Quartus II software to open it for modification, here we suggest also in the Quartus II software to modify. We find the [File] → [Open] button in the menu bar of the Quartus II software and open it, and find our Verilog file in the dialog box. After opening the figure, as shown in the figure, we can see that the Quartus II software has done some basic work for us, including the port code and the declaration of interface variables. All we have to do is add the test code we need to this template (that is, what we often call incentives). In order to enable readers to better understand the simulation, here we briefly introduce the TestBench source code: line 1 of the code, indicating that the unit time of the simulation is 1ps, and the precision is 1ps. If you want to carry out the simulation, you must first specify the time unit. We suggest that you should uniformly specify the time unit in Testbench, not in the engineering code, because different modules may bring some problems to the simulation if the time unit is different. Timescale is an incomprehensible syntax in Verilog syntax. Line 2 of the code is the part we are familiar with, where lines 5 to 10 are our data type definitions, where we can see that reg eachvec is an extra signal, which has no effect, and we can delete it. Next, let's look at lines 13 to 18, which is a module call that connects signals from our Verilog module to our TestBench module. Finally, let's look at lines 20 to 32, where lines 20 to 26 are the initialization of the signal, and lines 28 to 31 are the generation of the clock signal. Here we are mainly going to talk about whether # 10000 timescale represents delay 10000ps (that is, 10ns). The specific delay unit depends on how our timescale is set. At this point, the whole code has been introduced. After writing the simulation file, we need to configure the simulation function in the Quartus II software. We find the [Assigement] → [Settings] button in the menu bar of the Quartus II software interface and open it. On the open page, we find the Simulation on the left and click on it. As shown in the picture, we select "Compile Test bench", and then click the [Test Benches] button behind it. The "Test Benches" window shown in figure 2.9 appears (that is, the window above in the figure), and then we click the [New] button, and the "New Test Bench Settings" window appears as shown in the figure (that is, the window at the bottom of the figure).

On this page, we enter the TestBench module name into the edit bars of "Test bench name" and "Top level module in test bench". Then we add the simulation file to the "Test bench and simulation files" drop-down list box, as shown in the figure, click [Open]. Then click the [Add] button to add to the bottom list as shown in the figure. After we click the [OK] button, we can see that the information just added to the simulation file appears in the list of "Test benches" window shown in figure 2.12. At this point, we have added the simulation file, and then we click the [OK] button to return to our Quartus II software interface. At the beginning of the functional simulation, everything is ready but Dongfeng. After so many steps above, we have finally completed all the settings, and then we can carry out the simulation. Before we start the simulation, we need to note that the function we implement in the Quartus II software is LED flicker, and its interval is 1s, if we want to simulate this function. Then the lowest running time of our simulation software is 1s. This 1s clock is very short to us, but it is very long to the simulation software. Our simulation software unit is ps. In order to facilitate our simulation, here we need to change the Verilog code slightly, we need to change parameter SET_TIME_1S = 27Secretd50000000000; change it to parameter SET_TIME_1S = 27Secretd50; that is, change our original 1s clock to 1us. After the modification, we find the [Tools] → [Run Simulation Tool] → [RTL Simulation] button in the menu bar of the Quartus II software interface and click it, and the interface shown in figure 2.13 will appear. See here, perhaps some friends click [RTL Simulation] and do not appear Modelsim simulation window interface, but appear as shown in figure 2.14 interface.

This kind of error is mainly caused by the incorrect Modelsim path we set up before. how to solve this problem?

We tried to set the ModelSim-Altera path to C:\ altera\ 13.1\ modelsim_ase\ win32aloem\. Unlike what we just set, we added a backslash at the end of the path. At this time, we click the [RTL Simulation] button and the Modelsim simulation window interface will appear. What we need to explain here is that some computers can run without adding a backslash, while others cannot run without a backslash. In the Modelsim software startup process, we do not need any operation, it will automatically complete the simulation, and give the waveform we need, when the waveform appears, we can check the waveform to determine whether the design function is normal.

After reading the above, have you mastered how ModelSim cooperates with Quarus automatic simulation? If you want to learn more skills or want to know more about it, you are welcome to follow the industry information channel, thank you for reading!

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