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This article mainly introduces what is the difference between DCM/DLL/PLL/MMCM in FPGA. It is very detailed and has certain reference value. Friends who are interested must finish reading it.

For FPGA engineers, the word DCM/DLL/MMCM/PLL can be seen almost every day, but many people don't know the difference between them.

In Xilinx's FPGA, the clock manager is called Clock Management, or CMT for short. All the DCM/PLL/MMCM we use is included in the CMT.

DCM is used in earlier FPGA, such as Sparten-3 and Virtex-4, and later devices are no longer used. In Virtex-4, CMT includes a PLL and two DCM. The core of DCM is DLL, namely Delay Locked Loop, which is a digital module, which can generate clock, frequency division, frequency doubling and phase dynamic adjustment of different phases, but its accuracy is limited.

PLL is Phase Locked Loop, which everyone should be familiar with, clock frequency doubling, frequency division, phase adjustment and so on can all use PLL, and PLL is an analog circuit, it produces a frequency more prepared than DCM, jitter is also better, but PLL can not dynamically adjust the phase.

MMCM is Mixed Mode Clock Manager, and its official explanation is: This is a PLL with some small part of a DCM tacked on to do fine phase shifting (that's why its mixed mode-the PLL is analog, but the phase shift is digital). In other words, it adds the function of dynamic phase adjustment on the basis of PLL. Because PLL is a module circuit and dynamic phase modulation is a digital circuit, it is called Mixed Mode. MMCM is introduced in Virtex-6, and there is only MMCM in Virtex-6.

In 7 series and Ultrascale, MMCM and PLL exist at the same time. The 7s FPGA contains up to 24 CMT, with each CMT containing one MMCM and one PLL. In Ultrascale, a CMT contains a MMCM and two PLL.

The advantage of MMCM over PLL is that the phase can be adjusted dynamically, but the area occupied by PLL is smaller.

In Vivado, when using Clock Wizard, we can choose to use MMCM or PLL, and the difference between them is only the red box in the image below.

The above is all the content of this article entitled "what's the difference between DCM/DLL/PLL/MMCM in FPGA". Thank you for reading! Hope to share the content to help you, more related knowledge, welcome to follow the industry information channel!

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