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This article mainly introduces the relevant knowledge of Verilog loop sentence case analysis, the content is detailed and easy to understand, the operation is simple and fast, and has a certain reference value. I believe you will gain something after reading this Verilog loop sentence example analysis article. Let's take a look at it.

Keywords: while, for, repeat, forever

There are four types of Verilog loop statements, which are while,for,repeat and forever loops. Loop statements can only be used in always or initial blocks, but can contain delay expressions.

While cycle

The syntax format of the while loop is as follows:

While (condition) begin... End

The while loop abort condition is condition is false.

If the condition is already false when you start execution to the while loop, the loop statement will not be executed once.

Of course, when there is only one statement to execute, the keywords begin and end can be omitted.

When the following code is executed, counter executes 11 times.

Example

`timescale 1ns/1nsmodule test; reg [3:0] counter; initial begin counter ='b0; while (counterb1; endend / / stop the simulation always begin # 10; if ($time > = 1000) $finish; endendmodule

The simulation results are as follows:

For cycle

The syntax format of the for loop is as follows:

For (initial_assignment; condition; step_assignment) begin... End

Initial_assignment is the initial condition.

If condition is the termination condition and condition is false, you will jump out of the loop immediately.

Step_assignment assigns statements to procedures that change control variables, usually by increasing or decreasing the count of loop variables.

Generally speaking, because processes such as initial conditions and self-addition operations are already included in for loops, for loops are more compact than while loops, but for loops can not be used instead of while loops in all cases.

The following example of the for loop achieves the same effect as the example in the while loop. It should be noted that I = I + 1 cannot be written in the form of ibasket + like the C language, and I = I-1 cannot be written in the form of I -.

Example

/ / for loop statement integer I; reg [3:0] counter2; initial begin counter2 ='b0; for (iTuno; ib1; endendrepeat loop

The syntax format of the repeat loop is as follows:

Repeat (loop_times) begin... End

The function of repeat is to execute a fixed number of loops, and it cannot use a logical expression to determine whether the loop continues to execute, as while loops do. The number of repeat loops must be a constant, variable, or signal. If the number of cycles is a variable signal, the number of cycles is the value of the variable signal when the execution of the repeat loop is started. Even if the variable signal value represented by the number of cycles changes during execution, the number of repeat execution does not change.

The following repeat loop example achieves the same effect as the example in the while loop.

Example

/ / repeat loop statement reg [3:0] counter3; initial begin counter3 ='b0; repeat (11) begin / / repeat 11 times # 10; counter3 = counter3 + 1'b1; endend

The following example of a repeat loop implements the function of storing 8 consecutive pieces of data:

Example

Always @ (posedge clk or negedge rstn) begin j = 0; if (! rstn) begin repeat (8) begin buffer [j]'b0; / / No delay assignment, that is, simultaneous assignment of 0 j = j + 1; end end else if (enable) begin repeat (8) begin @ (posedge clk) buffer [j]

The simulation results are shown in the following figure.

As can be seen from the figure, when rstn is pulled up, the eight vectors of buffer are assigned to 0 at the same time.

After the second clock cycle, buffer is assigned by counter3 in turn, realizing the function of storing 8 data continuously.

Forever cycle

The syntax format of the forever loop is as follows:

Forever begin... End

The forever statement represents a permanent loop and does not contain any conditional expressions. Once executed, it will be executed indefinitely, and the system function $finish can exit forever.

Forever is equivalent to while (1).

Typically, forever loops are used in conjunction with timing control structures.

For example, use the forever statement to generate a clock:

Example

Reg clk; initial begin clk = 0; forever begin clk = ~ clk; # 5; endend

For example, use a forever statement to implement a clock edge-controlled inter-register data transfer function:

Example

Reg clk; reg data_in, data_temp; initial begin forever @ (posedge clk) data_temp = data_in; end's article on "instance Analysis of Verilog Loop sentences" ends here. Thank you for reading! I believe you all have a certain understanding of the knowledge of "case analysis of Verilog loop sentences". If you want to learn more, you are welcome to follow the industry information channel.

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