Shulou(Shulou.com)06/03 Report--

20. Create a professional compilation environment (1) _ module Makefile design 20.0. Experimental materials

Project architecture:

Please fill in the contents of each document by yourself.

20.1. Directory structure of large projects (no third-party libraries)

20.2. Analysis of Project Architecture Design

The project is divided into different modules:

Each module is managed by a folder, and the files are composed of inc, src and makefile.

The external functions of each module are placed in common/inc, such as common.h xxxfunc.h

20.3. Project goal

In an engineering project, you do not want the source folder to be changed at compile time (read-only folder)

Automatically create a folder (build) at compile time to hold the compilation results

In the process of compilation, the dependency relationship can be generated automatically and the required files can be searched automatically.

Each module can have its own independent compilation mode.

Support for debug versions and compilation options

20.4. Solution

The first phase: code compilation in each module is called a static library file (compile)

The second stage: finally link the static library file of each module into the final executable program (link)

20.5. First phase task

Complete the makefile file that can be used for compilation of each module

The compilation result of the completed module is a static library file (.a file).

20.5.1. Key implementation points

Automatically generate dependencies (gcc-MM)

Automatically search for required files (vpath)

Package the target file as a static library file (ar crs)

20.5.2. The composition of the module makefile

20.6. The final result

Large scale

.PHONY: allDIR_BUILD: = / root/w_share/DT/ToBeMaster/makefile/20/buildDIR_COMMON_INC: = / root/w_share/DT/ToBeMaster/makefile/20/common/incDIR_SRC: = srcDIR_INC: = incTYPE_INC: = .hTYPE _ SRC: = .cTYPE _ OBJ: = .oTYPE _ DEP: = .depar: = arARFLAGS: = crsCC: = gccCFLAGS: =-I $(DIR_INC)-I $(DIR_COMMON_INC) ifeq ($(DEBUG)) True) CFLAGS + =-gendifMODULE: = $(realpath.) MODULE: = $(notdir $(MODULE)) DIR_OUTPUT: = $(addprefix $(DIR_BUILD) /, $(MODULE)) OUTPUT: = $(MODULE). AOUTPUT: = $(addprefix $(DIR_BUILD) /, $(OUTPUT)) SRCS: = $(wildcard $(DIR_SRC) / * $(TYPE_SRC)) OBJS: = $(SRCS:$ (TYPE_SRC) = $(TYPE_OBJ)) OBJS: = $(patsubst $(DIR_SRC) /% $(DIR_OUTPUT) /%, $(OBJS) DEPS: = $(SRCS:$ (TYPE_SRC) = $(TYPE_DEP)) DEPS: = $(patsubst $(DIR_SRC) /%, $(DIR_OUTPUT) /%, $(DEPS)) vpath% $(TYPE_INC) $(DIR_INC) vpath% $(TYPE_INC) $(DIR_COMMON_INC) vpath% $(TYPE_SRC) $(DIR_SRC)-include $(DEPS) all: $(OUTPUT) @ echo "Success! Target = > $(OUTPUT) "$(OUTPUT): $(OBJS) $(AR) $(ARFLAGS) $@ $^ $(DIR_OUTPUT) /% $(TYPE_OBJ):% $(TYPE_SRC) $(CC) $(CFLAGS)-o $@-c $(filter% $(TYPE_SRC), $^) $(DIR_OUTPUT) /% $(TYPE_DEP):% $(TYPE_SRC) @ echo" Creating $@... "@ set-e \ $(CC) $(CFLAGS)-MM-E $(filter% $(TYPE_SRC), $^) | sed's,\ (.*\)\ .o [:] *, $(DIR_OUTPUT) /\ 1 $(TYPE_OBJ) $@:, g'> $@

Note: in the course of the experiment, you need to create the folder of build and each module, and change the absolute path in makefile to the path of your own code.

Output result:

Here we see that the dependent files and compiled files are successfully generated under build/common, and these .o files are packaged and placed in the build folder.

Think about it: how to write a project makefile so that it can trigger a call to the module makefile and eventually generate an executable program?

21. Create a professional compilation environment _ link 21.1. The second phase task

Complete the makefile file of the whole project; call makefile to compile and generate static library files; link the static library files of all modules to get the final executable program.

21.2. Key implementation points

How do I automatically create a build folder and its subfolders?

How to enter each module folder to compile?

How to connect all module static libraries after successful compilation?

21.3. Empirical assumptions in development

Each module in the project has been basically determined in the design phase, so it will not be increased or decreased frequently in the later development process.

21.4. Solution design

1. Define variable save module name

two。 Traversing module name variables using for loop in shell

3. Enter the module folder in the for loop to compile

4. Connect all module static library files at the end of the loop

For cycle sneaking into shell in 21.4.1.Makefile

21.4.2. Matters needing attention

When embedding shell code in Makefile, if you need to use the value of the shell variable, you must precede the variable with $$, such as $$dir, to distinguish it from a shell variable rather than a variable defined in Makefile.

21.4.3. For cycle experiment in shell

Compile: $(DIR_BUILD) $(DIR_BUILD_SUB) @ echo "Begin to compile." @ set-e;\ for dir in $(MODULES);\ do\ cd $$dir & & $(MAKE) all DEBUG:=$ (DEBUG) & & cd. ;\ done @ echo "Compile Success!"

Key components in Engineering makefile

Compile makefile:

.PHNY: all compileMODULES: = common\ module\ mainMKDIR: = mkdirRM: = rm-frDIR_PROJECT: = $(realpath.) DIR_BUILD: = buildDIR_BUILD_SUB: = $(addprefix $(DIR_BUILD) /, $(MODULES)) MODULE_LIB: = $(addsuffix .a, $(MODULES)) compile: $(DIR_BUILD) $(DIR_BUILD_SUB) @ echo "Begin to compile." @ set-e;\ for dir in $(MODULES) \ do\ cd $$dir & & $(MAKE) all DEBUG:=$ (DEBUG) & & cd. ;\ done @ echo "Compile Success!" $(DIR_BUILD) $(DIR_BUILD_SUB): $(MKDIR) $@

Output result:

Compiled successfully, the package files of each module are generated under the build folder.

21.5. Considerations when linking

Gcc must follow strict dependencies when making static library connections.

Gcc-o app.out x.a y.a

The dependency must be: x.a-> y.a, y.a-> z.a

Follow a left-to-right dependency by default

If you are not aware of the dependencies between libraries, you can use-Xlinker to determine the dependencies automatically

Gcc-o app.out-Xlinker "- (" z.a y.a x.a-Xlinker "-)" link $(APP): $(MODULE_LIB) @ echo "Begin to link..." $(CC)-o $(APP)-Xlinker "- (" $^-Xlinker "-)" $(LFLAGS) @ echo "Link Success!" 21.6. Final solution .PHONY: all compile link clean rebuildMODULES: = common\ module\ mainMKDIR: = mkdirRM: = rm-frCC: = gccLFLAGS: = DIR_PROJECT: = $(realpath.) DIR_BUILD: = buildDIR_BUILD_SUB: = $(addprefix $(DIR_BUILD) /, $(MODULES)) MODULE_LIB: = $(addsuffix .a, $(MODULES)) MODULE_LIB: = $(addprefix $(DIR_BUILD) / (MODULE_LIB) APP: = app.outAPP: = $(addprefix $(DIR_BUILD) /, $(APP)) all: compile $(APP) @ echo "Success! Target = > $(APP) "compile: $(DIR_BUILD) $(DIR_BUILD_SUB) @ echo" Begin to compile... "@ set-e;\ for dir in $(MODULES);\ do\ cd $$dir & & $(MAKE) all DEBUG:=$ (DEBUG) & & cd. \ done @ echo "Compile Success!" link $(APP): $(MODULE_LIB) @ echo "Begin to link..." $(CC)-o $(APP)-Xlinker "- (" $^-Xlinker "-)" $(LFLAGS) @ echo "Link Success!" $(DIR_BUILD) $(DIR_BUILD_SUB): $(MKDIR) $@ clean: @ echo "Begin to clean..." (RM) $(DIR_BUILD) @ echo "Clean Success!" rebuild: clean all

Think about:

Are there any potential problems with the current makefile of the entire project? Do you need refactoring?

twenty-two。 Create a professional compilation environment (compilation environment refactoring)

Are there any potential problems with the current makefile of the entire project? Do you need refactoring?

22.1. Absolute path problem

All the compilation paths used in makefile are absolute paths written to death. Once the project file is moved, the compilation will fail!

22.1.1. Solution:

Obtain the source code path of the project in the project makefile, according to the project source code path:

Splice the path to the compiled folder (DIR_BUILD)

Stitching to get the global inclusion path (DIR_COMMON_INC)

Pass the path to the module makefile through the command line variable

Compile: $(DIR_BUILD) $(DIR_BUILD_SUB) @ echo "Begin to compile..." @ set-e;\ for dir in $(MODULES) \ do\ cd $$dir & &\ $(MAKE) all\ DEBUG:=$ (DEBUG)\ DIR_BUILD:=$ (addprefix $(DIR_PROJECT) /, $(DIR_BUILD))\ DIR_COMMON_INC:=$ (addprefix $(DIR_PROJECT) /, $(DIR_COMMON_INC)) & &\ cd. ;\ done @ echo "Compile Success!" 22.2. Code reuse problem (module makefile refactoring)

The content of all modules makefile is exactly the same!

When the module makefile needs to be changed, multiple identical changes will be involved!

22.2.1. Solution

Split the module makefile into two template files

Mod-cfg.mk: define variables that may change

Mod-rule.mk: define relatively stable variables and rules

By default, the module makefile reuses template files to implement the function (include)

22.2.2. Solution

How does the module makefile guide the specific location of the template file?

Pass the location of the template file through the command line variable

$(MAKE) all\ DEBUG:=$ (DEBUG)\ DIR_BUILD:=$ (addprefix $(DIR_PROJECT) /, $(DIR_BUILD))\ DIR_COMMON_INC:=$ (addprefix $(DIR_PROJECT) /, $(DIR_COMMON_INC))\ CMD_CFG:=$ (addprefix $(DIR_PROJECT) / CMD_CFG)\ MOD_CFG:=$ (addprefix $(DIR_PROJECT) /, $(MOD_CFG))\ MOD_RULE:=$ (addprefix $(DIR_PROJECT) /, $(MOD_RULE)) & &\

Final plan:

Module makefile:

Include $(MOD_CFG) # these configurations are retained here rather than deleted directly, because we may need to make a special configuration for a module, so we only need to change it here # Custmization Begin# # DIR_SRC: = src# DIR_INC: = .h # TYPE_SRC: = .c # TYPE_OBJ: = .o # TYPE_DEP: = .dep # # Custmization Endinclude $(CMD_CFG) include $(MOD_RULE)

The sub-module mod-cfg.mk contained in the include in the module makefile:

DIR_SRC: = srcDIR_INC: = incTYPE_INC: = .hTYPE _ SRC: = .cTYPE _ OBJ: = .oTYPE _ DEP: = .dep

The sub-module mod-rule.mk contained in the include in the module makefile:

# generate dependent files and compile Package .PHONY: allMODULE: = $(realpath.) MODULE: = $(notdir $(MODULE)) DIR_OUTPUT: = $(addprefix $(DIR_BUILD) /, $(MODULE)) OUTPUT: = $(MODULE). AOUTPUT: = $(addprefix $(DIR_BUILD) /, $(OUTPUT)) SRCS: = $(wildcard $(DIR_SRC) / * $(TYPE_SRC) OBJS: = $(SRCS:$ (TYPE_SRC) = $(TYPE_OBJ) OBJS: = $(patsubst $(DIR_SRC) /%) $(DIR_OUTPUT) /%, $(OBJS) DEPS: = $(SRCS:$ (TYPE_SRC) = $(TYPE_DEP)) DEPS: = $(patsubst $(DIR_SRC) /%, $(DIR_OUTPUT) /%, $(DEPS)) vpath% $(TYPE_INC) $(DIR_INC) vpath% $(TYPE_INC) $(DIR_COMMON_INC) vpath% $(TYPE_SRC) $(DIR_SRC)-include $(DEPS) all: $(OUTPUT) @ echo "Success! Target = > $(OUTPUT) "$(OUTPUT): $(OBJS) $(AR) $(ARFLAGS) $@ $^ $(DIR_OUTPUT) /% $(TYPE_OBJ):% $(TYPE_SRC) $(CC) $(CFLAGS)-o $@-c $(filter% $(TYPE_SRC), $^) $(DIR_OUTPUT) /% $(TYPE_DEP):% $(TYPE_SRC) @ echo" Creating $@... "@ set-e \ $(CC) $(CFLAGS)-MM-E $(filter% $(TYPE_SRC), $^) | sed's,\ (.*\)\ .o [:] *, $(DIR_OUTPUT) /\ 1 $(TYPE_OBJ) $@:, g'> $@

The sub-module cmd-cfg.mk contained in the include in the module makefile:

AR: = arARFLAGS: = crsCC: = gccLFLAGS: = CFLAGS: =-I $(DIR_INC)-I $(DIR_COMMON_INC) ifeq ($(DEBUG), true) CFLAGS + =-gendifMKDIR: = mkdirRM: = rm-fr22.3. Reconstruction of Engineering makefile

Split command variables, project variables, and other variables and rules into different files

Cmd-cfg.mk: define variables related to a command

Pro-cfg.mk: define project variables, compilation path variables, etc.

Pro-rule.mk: define additional variables and rules

The final makefile is formed by including the split file (include)

Final plan:

Project Master makefile:

Include pro-cfg.mkinclude cmd-cfg.mkinclude pro-rule.mk

The sub-module pro-cfg.mk contained in the include in the project makefile:

MODULES: = common\ module\ mainMOD_CFG: = mod-cfg.mkMOD_RULE: = mod-rule.mkCMD_CFG: = cmd-cfg.mkDIR_BUILD: = buildDIR_COMMON_INC: = common/incAPP: = app.out

The sub-module pro-rele.mk contained in the include in the project makefile:

.PHONY: all compile link clean rebuildDIR_PROJECT: = $(realpath.) DIR_BUILD_SUB: = $(addprefix $(DIR_BUILD) /, $(MODULES)) MODULE_LIB: = $(addsuffix .a, $(MODULES)) MODULE_LIB: = $(addprefix $(DIR_BUILD) /, $(MODULE_LIB)) APP: = $(addprefix $(DIR_BUILD) /, $(APP)) all: compile $(APP) @ echo "Success! Target = > $(APP) "compile: $(DIR_BUILD) $(DIR_BUILD_SUB) @ echo" Begin to compile... "@ set-e;\ for dir in $(MODULES) \ do\ cd $$dir & &\ $(MAKE) all\ DEBUG:=$ (DEBUG)\ DIR_BUILD:=$ (addprefix $(DIR_PROJECT) /, $(DIR_BUILD))\ DIR_COMMON_INC:=$ (addprefix $(DIR_PROJECT) / (DIR_COMMON_INC))\ CMD_CFG:=$ (addprefix $(DIR_PROJECT) /, $(CMD_CFG))\ MOD_CFG:=$ (addprefix $(DIR_PROJECT) /, $(MOD_CFG))\ MOD_RULE:=$ (addprefix $(DIR_PROJECT) /, $(MOD_RULE)) & &\ cd. \ done @ echo "Compile Success!" link $(APP): $(MODULE_LIB) @ echo "Begin to link..." $(CC)-o $(APP)-Xlinker "- (" $^-Xlinker "-)" $(LFLAGS) @ echo "Link Success!" $(DIR_BUILD) $(DIR_BUILD_SUB): $(MKDIR) $@ clean: @ echo "Begin to clean..." (RM) $(DIR_BUILD) @ echo "Clean Success!" rebuild: clean all22.4. Summary

The compilation environment of large projects is made up of different makefile.

The design of the compilation environment needs to be based on the overall architecture of the project.

The compilation process of the whole project can be broken down into different phases.

Makefile is designed according to different stages.

Makefile should also consider basic program features such as reusability and maintainability.

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