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This article mainly explains "how to understand the memory order of C++". The content in the article is simple and clear, and it is easy to learn and understand. Please follow the editor's train of thought to study and learn "how to understand the memory order of C++".

Key Points:

In a word, memory_orderrelease semantics should be understood from the perspectives of "preventing compiler rearrangement" and "preventing CPU disorder". Generally speaking, it means "last Store" acquire semantics in a nutshell, and generally means "first Load" note: x86 CPU 64 CPU generally satisfies the strong memory model feature: among the four possible CPU disorder, only StoreLoad disorder (or StoreLoad rearrangement) is allowed.

1) used with atomic

What is the difference between the relaxed operation of memory_order_relaxed:atomic variable and the normal operation of ordinary variables?

The SL operations of ordinary variables do not guarantee atomicity, while all operations of atomic variables are guaranteed atomicity. (TODO: won't even be interrupted?) X86164Measurement: the atomic variable combined with any memory_order can effectively prevent compiler rearrangement.

Memory_order_consume: all subsequent data-dependent re-order L operations are prohibited in front of this L. Used with release-S.

Memory_order_acquire: all subsequent Splash L operations are prohibited from being re-order in front of this L. Used with release-S.

The acquire operation emphasizes that this L must be the "first Load".

X860064 measured:

A.load (acquire/relaxed) produces the same machine code. The guess is that because of the strong-memory-model nature of x86q64, rearrangement of LMui S and LMI L is prohibited, and any Load has acquire semantics. UB operation: a.store (acquire), then the machine code will add a mfence after S. The actual semantics generated at this time is: all subsequent Sripple L operations are prohibited from being re-order in front of this S. The guess is that x86 colors 64 CPU allows Smurl re-order, so you can only add the fence instruction to ensure that the Smell following this S is not rearranged before this S. UB operation: the machine code generated by a.load (release) is equivalent to a.load (acquire). (note that it does not match the semantics similar to S-release. "all previous a.load L operations are prohibited from being re-order after this L, and must be preceded by mfence if they are to be met.)" UB operation: a.load () and all memory_order are equivalent to a.load (acquire), that is, compiling to produce the same machine code.

Memory_order_release: all previous Splash L operations are prohibited from being re-order to the back of this S. Used with acquire/consume-L.

The release operation emphasizes that this S operation must be the "last Store".

X860064 measured:

A.store (release/relaxed) produces the same machine code. The guess is that the rearrangement of S-S and L-S is prohibited because of the strong-memory-model nature of x86room64, and any Store has release semantics. UB operation: the machine code generated by a.store (acquire/consume/acq_rel/seq_cst) is the same, adding a mfence instruction after this S. The guess is that in x86 / 64, only a mfence needs to be added after S, and the S can satisfy both the two conditions that "all S picks L before this S are forbidden to be rescheduled after this S (that is, release semantics)" and "all S Unix L after this S is prohibited to be rearranged before this S (similar to L-acquire semantics)".

Memory_order_acq_rel: suitable for RMW operations.

1) all Sramp L operations of this thread (whether before or after) are prohibited by re-order before or after this S. Why only mention S? TODO: does this RMW operation have to be atomic? In fact, you only need to care about S. Because the characteristic of RMW operation is similar to that of a LS operation, S has been used as the synchronization point, and even if the Sdebar L before this thread L is rearranged, it can only be rearranged after this L and before this S, even if such a rearrangement occurs. However, after this S, all S _ big L can not be rescheduled before this S, which indirectly ensures that it can not be rearranged before this L, thus ensuring the semantics of acquire. 2) for other threads that perform the corresponding release operation, all S before the release must occur before this S. This sentence actually implies that the S of the atomic variable itself caused by other threads must have occurred before this L. Because if the changes made by other threads to the atomic variable have not been observed by this thread, it can be assumed that other threads have not written it, and there is no synchronization problem. Now that a change has been observed, the order of changes that accompany the change needs to be discussed. Because S is slower than L, this semantics only requires that the S of other threads being release must occur before this S, and there is no need to be so strict that it must occur before this L, so the efficiency will become less efficient. However, this requirement is more stringent than the simple acquire, that is, it requires that the S of other threads being release can occur after this L but must occur before this S, while the simple acquire only implies this L, you can see that all the relevant threads have been used by the S of release: xthread 1; y.store (1, release); at this time, these S, which are called xthread 1 and release 1, finally perform the release operation. In other words, both xroom1 and yroom1 are the S operations of the thread release, and the synchronization point is Y.

Memory_order_seq_cst:

Execute acquire semantics for L, execute release semantics for S, execute acq_rel semantics for RMW, and perform seq_cst operations on all threads S, there is a TSOTSO:Total Single Order, and all threads observe the same S order? X86164Measurement: when seq_cst is used with load operation, it is equivalent to all memory_order. That is, compiling to produce the same machine code. Seq_cst is equivalent to acquire/consume/acq_rel when used with a store operation. Thank you for your reading, the above is the content of "how to understand the memory order of C++". After the study of this article, I believe you have a deeper understanding of how to understand the memory order of C++, and the specific use needs to be verified in practice. Here is, the editor will push for you more related knowledge points of the article, welcome to follow!

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