Shulou(Shulou.com)06/01 Report--

In this issue, the editor will bring you about the manual timing simulation of modelsim. The article is rich in content and analyzes and narrates it from a professional point of view. I hope you can get something after reading this article.

The steps of timing simulation and functional simulation are roughly the same, except that simulation libraries, Netlist (.vo) files and delay (.sdo) files need to be added in the middle. At this point, the question is, how can simulation libraries, Netlist (.vo) files and delay (.sdo) files be obtained? Netlist (.vo) file and delay (.sdo) file, in fact, we have generated in the automatic simulation configuration simulation function, when we configure the simulation function, we do a full compilation in Quartus, at this time, we open the Quartus project directory in simulation/modelsim, we can see Verilog_First.vo and Verilog_First_v.sdo these two files. We copy these two files to our manual_modelsim folder. Simulation library, we need to go to our Altera installation directory, that is, C:\ altera\ 13.1\ modelsim_ase\ altera\ verilog to find the cycloneive folder, and then we will copy the cycloneive folder to our manual_modelsim folder. Everything is ready, and then we can open our ModelSim software, as shown in the figure

From the diagram, we can see that this project is our previous functional simulation project. When we close ModelSim, we open the ModelSim software again, and it will automatically record the last project we used and open it. We will make changes directly on this project. First, we right-click to find the [Add to Project] → [Existing File...] button in the pop-up menu bar and click to open, then the pop-up image will appear.

In this dialog box we click [Browse], in the pop-up dialog box we find the Verilog_First.vo under the manual_modelsim folder, and then add Verilog_First.vo to our ModelSim simulation project. Next, we compile the code. After the compilation is complete, we find the [Simulate] → [StartSimulation...] button in the menu bar of ModelSim and click Open. We open the Libraries tab and add the simulation library to the configuration simulation environment. As shown in the figure here, we need to note that adding only one cycloneive simulation library is not enough, we also need to add the altera_ver library in our ModeSim simulation library. If we don't know which library to choose, we can run the simulation directly. At this time, an error message will be prompted in the ModelSim control window, and we will be able to analyze the name of the library we need according to the error message. Then we repeat the above steps to add the simulation library, and then we add the Verilog_First_v.sdo file to the SDF tag page. Here is what we need to pay attention to. Because our instance alias is i1, we fill in / i1. After the addition is completed, we return to the Design tag page and find the Verilog_First_vlg_tst under work. As shown in the figure on this page, we can click "OK" to start timing simulation. The above is the manual timing simulation of modelsim shared by Xiaobian. If you happen to have similar doubts, you might as well refer to the above analysis to understand. If you want to know more about it, you are welcome to follow the industry information channel.

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