Shulou(Shulou.com)06/02 Report--

I. the use of cross-compilation tools

In the embedded development of  , there are usually two roles: host and target. The host is the computer that compiles and links the embedded software, and the target is the hardware platform that runs the embedded software. Sometimes the hardware / software platforms may be different between the two, and programs that directly use the compiler on the host cannot run on the target machine, so cross-compilation tools appear. For the Linux target machine running on the ARM architecture, the special cross-compilation tools are arm-linux-gcc, arm-linux-ld and so on.

  A C _ preprocessing + file must be preprocessed (preprocessing), compiled (compilation), assembled (assembly) and linked (linking) before it can become an executable file. The role of each step is described in the following table:

Step instructions in preprocessing the source file, commands that begin with "#" are called preprocessing commands, such as including commands "# include", "# define", "# if", "# ifdef" and so on. Preprocessing is to insert the file that will contain (include) into the original file, expand the macro definition, select the code to use according to the conditional compilation command, and finally output these things to an ".i" file for further processing. To compile and compile is to "translate" the CCompact + code (such as the ".i" file above) into assembly code. Assembler is to translate the assembly code output from the second step into machine code in accordance with a certain format, which is generally represented as ELF object files (OBJ files) on Linux systems. The link link is to connect the OBJ file generated in the previous step with the OBJ file and library file of the system library, and finally generate an executable file that can be run on a specific platform.

The   compiler uses one or more of the above four steps to process the input file, the suffix of the source file indicates the language used by the source file, and the suffix controls the default action of the compiler.

Suffix name language category .cC source program .I preprocessed c file .s or .s assembly language source program .h header file .o assembled object file, contains entry marks and descriptions of each function, and needs to be linked (link) when the program is to be executed. A link is to chain multiple .o files into an executable file.

The commands that   often uses in cross-compilation tools are:

Command introduces arm-linux-gcc compiler arm-linux-ld linker arm-linux-objdump disassembly tool arm-linux-readelfelf file viewer arm-linux-objcopy file conversion tool

1.arm-linux-gcc

Common options:

-E: let the compiler stop the compilation process after preprocessing.-o file: specify the output file as file-S: compile instead of assemble, generate assembly code-c: convert assembly code to binary object code of ".o" (- c can complete the first three tasks at once)

2.arm-linux-ld

Used to connect multiple target files and library files into executable files, common options:

Object-file-name: the default is an OBJ file or a library file (the connector can distinguish between OBJ files and library files based on the contents of the file). If GCC performs a connection operation, these OBJ files become input files for the connector. -llibrary: connect to the library file named library. -nostdlib: do not connect the system standard startup file and the standard library file, only pass the specified file to the connector. This option is often used to compile programs such as kernel, bootloader, and so on, which do not require startup files or standard library files. -static: prevents connections to shared libraries on systems that support dynamic connection (dynamic linking). -shared: generates a shared OBJ file that can be connected to other OBJ files to produce executable files. Only some systems support this option. -T: only connect to software that is not supported by the underlying software, such as Bootloader, kernel, etc.; you do not need to specify-T when connecting applications running on the operating system.

3.arm-linux-objcopy

It is used to copy the contents of one target file to another file, and the destination file can be output in a format different from that of the source file, that is, the format can be converted.

Input-file, outfile: input target file (source target file) and output target file (destination target file)-I bfdname: used to indicate the format of the source file, bfdname is the standard format name described in the BFD library-O bfdname: export the file using the specified format Bfdname is the standard format name described in the BFD library-F bfdname: indicates the format of both the source file and the destination file-R sectionname: deletes all segments named sectionname from the output file. -S: do not copy relocation information and symbol information from the source file to the target file-g: do not copy debug symbols from the source file to the target file

When compiling bootloader and kernel, arm-linux-objcopy commands are commonly used to convert the generated results in ELF format into binary files, such as:

$arm-linux-objcopy-O binary-S elf_file bin_file

4.arm-linux-objdump

Used to display binary file information.

-b bfdname: specifies the object code format. You can use the "arm-linux-objdump-I" command to view a list of supported object code formats. -disassemble: disassemble executable segment (executable sections). -disassemble-all: similar to-d, disassemble all segments. -EB: specifies the byte order. -- file-headers: displays the overall header summary information of the file. -- section-headers: displays the header summary information of each segment of the target file. -info: displays supported target file formats and CPU schemas, which are used in the "- b" and "- m" options. -- section=name: displays only the information for the specified section. -- architecture=machine: specifies the schema to use when disassembling the target file, which is useful when the disassembly file itself does not describe the schema information (such as S-records).

5.arm-linux-readelf

-an application can view information such as file running architecture, size, shared libraries, and so on. Applications that add the "- static" option at compile time. -d applications can view the dynamic link libraries of applications II. Makefile project manager

  when a project consists of hundreds of files of code, if only one or a few files have been modified, use the Gcc compilation tool, you will have to recompile all the files, because the compiler does not know which files are recently updated, only all re-can get executable files.

However, the compilation process of   is divided into different stages of compilation, assembly and linking, in which the compilation phase only checks whether the syntax errors and the declaration of functions and variables are declared correctly, and in the linking phase, it mainly completes the linking of functions and global variables. Therefore, the source code that has not been changed does not need to be recompiled at all, just re-link them in. On the other hand, the Make project manager can automatically recognize the updated file code without the need to repeatedly enter a lengthy command line.

The   Make project manager is also an "automatic compilation manager", which can automatically find updated files according to the file timestamp to reduce the compilation workload. At the same time, it performs a lot of compilation work by reading the contents of Makefile files.

The composition of 1.Makefile

  Makefile is the only configuration file that Make reads, and usually contains the following in a Makefile:

A target body (target) that needs to be created by the make tool, usually an object file or executable file

The file on which the target body to be created depends (dependency_file)

The command (command) that needs to be run when creating each target body.

Target: dependency_files command such as: hello.o: hello.c hello.h gcc-c hello.c-o hello.o

Variables of 2.Makefile

The   variable is the name defined in Makefile to replace a text string called the value of the variable. Under specific requirements, these values can replace the target body, dependent files, commands, and other parts of the makefile file. There are two ways to define variables in Makefile: one is recursive expansion, and the other is simple.

The variable defined by the recursive expansion method of   is replaced when referencing the variable, that is, if the variable contains the application of other variables, then all the embedded variables are expanded at once when referencing the variable. The disadvantage is that the content cannot be appended after the variable (because the statement: CFLAGS = $(CFLAGS)-O may cause an infinite loop in the process of variable expansion). The value of a simple extended variable expands at the definition and only once, so it does not contain any references to other variables, eliminating nested references to variables.

The definition format of the recursive expansion method is: VAR=var.

The definition format of simple extension method is: VAR:=var.

Variables in Make are used in the format: $(VAR).

  predefined variables contain the names of common compilers, assemblers, and their compilation options:

Command format means the name of the AR library file maintenance program, the default value is the name of the arAS assembler, the default value is the name of the asCCC compiler, the default value is the name of the ccCPPC precompiler, the default value is $(CC)-the name of the ECXXC++ compiler, the default value is the name of the g++FCFORTRAN compiler, the default value is the name of the f77RM file deletion program, the default value is the rm-fARFLAGS library file maintenance program option, no default value ASFLAGS assembler option No default CFLAGSC compiler options, no default CPPFLAGSC precompiled options, no default CXXFLAGSC++ compiler options, no default FFLAGSFORTRAN compiler options, no default values

Common automatic variables in Makefile

The imperative format contains meaning $* the name of the target file that does not contain the extension $+ all dependent files, separated by spaces and in order of occurrence, may contain duplicate dependent files $

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